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    Semiconductor device and method of forming conductive vias by backside via reveal with CMP
    2.
    发明授权
    Semiconductor device and method of forming conductive vias by backside via reveal with CMP 有权

    公开(公告)号：US10115701B2

    公开(公告)日：2018-10-30

    申请号：US14316561

    申请日：2014-06-26

    Applicant: STATS ChipPAC, Ltd.

    Inventor： Xing Zhao ,  Duk Ju Na ,  Siew Joo Tan ,  Pandi C. Marimuthu

    IPC: H01L25/065 ,  H01L23/00 ,  H01L21/78 ,  H01L21/768 ,  H01L25/00

    Abstract: A semiconductor device has a semiconductor wafer and a conductive via formed through the semiconductor wafer. A portion of the semiconductor wafer is removed such that a portion of the conductive via extends above the semiconductor wafer. A first insulating layer is formed over the conductive via and semiconductor wafer. A second insulating layer is formed over the first insulating layer. The first insulating layer includes an inorganic material and the second insulating layer includes an organic material. A portion of the first and second insulating layers is removed simultaneously from over the conductive via by chemical mechanical polishing (CMP). Alternatively, a first insulating layer including an organic material is formed over the conductive via and semiconductor wafer. A portion of the first insulating layer is removed by CMP. A conductive layer is formed over the conductive via and first insulating layer. The conductive layer is substantially planar.

    Semiconductor Device and Method of Wafer Thinning Involving Edge Trimming and CMP
    6.
    发明申请
    Semiconductor Device and Method of Wafer Thinning Involving Edge Trimming and CMP 有权
    半导体器件和涉及边缘修整和CMP的晶片薄化的方法

    公开(公告)号：US20150179544A1

    公开(公告)日：2015-06-25

    申请号：US14134907

    申请日：2013-12-19

    Applicant: STATS CHIPPAC, LTD.

    Inventor： Vinoth Kanna Chockanathan ,  Xing Zhao ,  Duk Ju Na ,  Chang Bum Yong

    IPC: H01L23/48 ,  H01L21/3105 ,  H01L23/31 ,  H01L21/56 ,  H01L21/306

    CPC classification number: H01L21/30625 ,  H01L21/304 ,  H01L21/31058 ,  H01L21/56 ,  H01L21/561 ,  H01L21/565 ,  H01L21/76898 ,  H01L21/78 ,  H01L23/3114 ,  H01L2224/16225 ,  H01L2224/48091 ,  H01L2224/73265 ,  H01L2924/15311 ,  H01L2924/00014

    Abstract: A semiconductor device has a substrate including a plurality of conductive vias formed vertically and partially through the substrate. An encapsulant is deposited over a first surface of the substrate and around a peripheral region of the substrate. A portion of the encapsulant around the peripheral region is removed by a cutting or laser operation to form a notch extending laterally through the encapsulant to a second surface of the substrate opposite the first surface of the substrate. A first portion of the substrate outside the notch is removed by chemical mechanical polishing to expose the conductive vias. A second portion of the substrate is removed by backgrinding prior to or after forming the notch. The encapsulant is coplanar with the substrate after revealing the conductive vias. The absence of an encapsulant/base material interface and coplanarity of the molded substrate results in less over-etching or under-etching and fewer defects.

    Abstract translation: 半导体器件具有包括垂直且部分穿过衬底形成的多个导电通孔的衬底。 密封剂沉积在衬底的第一表面上并且围绕衬底的周边区域。 通过切割或激光操作去除围绕周边区域的密封剂的一部分，以形成横向延伸通过密封剂的凹口到衬底的与衬底的第一表面相对的第二表面。 通过化学机械抛光去除凹口外部的基板的第一部分以暴露导电通孔。 在形成凹口之前或之后，通过背面研磨去除衬底的第二部分。 透明导电孔之后，密封剂与基板共面。 密封剂/基材界面的不存在和模塑基材的共面性导致较少的过蚀刻或欠蚀刻和较少的缺陷。

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