公开(公告)号：US20150179544A1

公开(公告)日：2015-06-25

申请号：US14134907

申请日：2013-12-19

Applicant: STATS CHIPPAC, LTD.

Inventor： Vinoth Kanna Chockanathan ,  Xing Zhao ,  Duk Ju Na ,  Chang Bum Yong

IPC: H01L23/48 ,  H01L21/3105 ,  H01L23/31 ,  H01L21/56 ,  H01L21/306

CPC classification number: H01L21/30625 ,  H01L21/304 ,  H01L21/31058 ,  H01L21/56 ,  H01L21/561 ,  H01L21/565 ,  H01L21/76898 ,  H01L21/78 ,  H01L23/3114 ,  H01L2224/16225 ,  H01L2224/48091 ,  H01L2224/73265 ,  H01L2924/15311 ,  H01L2924/00014

Abstract: A semiconductor device has a substrate including a plurality of conductive vias formed vertically and partially through the substrate. An encapsulant is deposited over a first surface of the substrate and around a peripheral region of the substrate. A portion of the encapsulant around the peripheral region is removed by a cutting or laser operation to form a notch extending laterally through the encapsulant to a second surface of the substrate opposite the first surface of the substrate. A first portion of the substrate outside the notch is removed by chemical mechanical polishing to expose the conductive vias. A second portion of the substrate is removed by backgrinding prior to or after forming the notch. The encapsulant is coplanar with the substrate after revealing the conductive vias. The absence of an encapsulant/base material interface and coplanarity of the molded substrate results in less over-etching or under-etching and fewer defects.

Abstract translation: 半导体器件具有包括垂直且部分穿过衬底形成的多个导电通孔的衬底。 密封剂沉积在衬底的第一表面上并且围绕衬底的周边区域。 通过切割或激光操作去除围绕周边区域的密封剂的一部分，以形成横向延伸通过密封剂的凹口到衬底的与衬底的第一表面相对的第二表面。 通过化学机械抛光去除凹口外部的基板的第一部分以暴露导电通孔。 在形成凹口之前或之后，通过背面研磨去除衬底的第二部分。 透明导电孔之后，密封剂与基板共面。 密封剂/基材界面的不存在和模塑基材的共面性导致较少的过蚀刻或欠蚀刻和较少的缺陷。

公开(公告)号：US09728415B2

公开(公告)日：2017-08-08

申请号：US14134907

申请日：2013-12-19

Applicant: STATS ChipPAC, Ltd.

Inventor： Vinoth Kanna Chockanathan ,  Xing Zhao ,  Duk Ju Na ,  Chang Bum Yong

IPC: H01L23/52 ,  H01L21/306 ,  H01L21/56 ,  H01L21/78 ,  H01L21/304 ,  H01L21/768 ,  H01L21/3105 ,  H01L23/31

CPC classification number: H01L21/30625 ,  H01L21/304 ,  H01L21/31058 ,  H01L21/56 ,  H01L21/561 ,  H01L21/565 ,  H01L21/76898 ,  H01L21/78 ,  H01L23/3114 ,  H01L2224/16225 ,  H01L2224/48091 ,  H01L2224/73265 ,  H01L2924/15311 ,  H01L2924/00014

Abstract: A semiconductor device has a substrate including a plurality of conductive vias formed vertically and partially through the substrate. An encapsulant is deposited over a first surface of the substrate and around a peripheral region of the substrate. A portion of the encapsulant around the peripheral region is removed by a cutting or laser operation to form a notch extending laterally through the encapsulant to a second surface of the substrate opposite the first surface of the substrate. A first portion of the substrate outside the notch is removed by chemical mechanical polishing to expose the conductive vias. A second portion of the substrate is removed by backgrinding prior to or after forming the notch. The encapsulant is coplanar with the substrate after revealing the conductive vias. The absence of an encapsulant/base material interface and coplanarity of the molded substrate results in less over-etching or under-etching and fewer defects.

公开(公告)号：US09837336B2

公开(公告)日：2017-12-05

申请号：US14257850

申请日：2014-04-21

Applicant: STATS ChipPAC, Ltd.

Inventor： Won Kyoung Choi ,  Chang Bum Yong ,  Jae Hun Ku

IPC: H01L23/48 ,  H01L23/31 ,  H01L21/683 ,  H01L25/065 ,  H01L21/768 ,  H01L23/00

CPC classification number: H01L23/481 ,  H01L21/6836 ,  H01L21/768 ,  H01L21/76898 ,  H01L23/3178 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L25/0657 ,  H01L2221/6834 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/05578 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/05669 ,  H01L2224/05671 ,  H01L2224/05681 ,  H01L2224/05684 ,  H01L2224/05686 ,  H01L2224/06181 ,  H01L2224/11334 ,  H01L2224/1146 ,  H01L2224/11849 ,  H01L2224/13025 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16146 ,  H01L2224/73104 ,  H01L2224/73204 ,  H01L2224/81005 ,  H01L2224/81191 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/01322 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/13091 ,  H01L2224/11 ,  H01L2924/01082 ,  H01L2924/04953 ,  H01L2924/01023 ,  H01L2224/05664 ,  H01L2924/01029 ,  H01L2924/01074 ,  H01L2924/01007 ,  H01L2224/03 ,  H01L2924/00 ,  H01L2224/05552

Abstract: A semiconductor device has a plurality of conductive vias formed into a semiconductor wafer. A portion of the semiconductor wafer is removed so the conductive vias extend above a surface of the semiconductor wafer. A notch is formed in the semiconductor wafer around each of the conductive vias. The notch around the conductive vias can be formed by wet etching, dry etching, or LDA. A first insulating layer is formed over a surface of the semiconductor wafer and conductive vias and into the notch to provide stress relief between the conductive vias and semiconductor wafer. A portion of the first insulating layer is removed to expose the conductive vias. A first conductive layer and second insulating layer can be formed around the conductive vias. A second conductive layer can be formed over the conductive vias. The notch can extend into the second insulating layer.

公开(公告)号：US20140225279A1

公开(公告)日：2014-08-14

申请号：US14257850

申请日：2014-04-21

Applicant: STATS ChipPAC, Ltd.

Inventor： Won Kyoung Choi ,  Chang Bum Yong ,  Jae Hun Ku

IPC: H01L23/48 ,  H01L21/768

CPC classification number: H01L23/481 ,  H01L21/6836 ,  H01L21/768 ,  H01L21/76898 ,  H01L23/3178 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L25/0657 ,  H01L2221/6834 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/05578 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/05669 ,  H01L2224/05671 ,  H01L2224/05681 ,  H01L2224/05684 ,  H01L2224/05686 ,  H01L2224/06181 ,  H01L2224/11334 ,  H01L2224/1146 ,  H01L2224/11849 ,  H01L2224/13025 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16146 ,  H01L2224/73104 ,  H01L2224/73204 ,  H01L2224/81005 ,  H01L2224/81191 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/01322 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/13091 ,  H01L2224/11 ,  H01L2924/01082 ,  H01L2924/04953 ,  H01L2924/01023 ,  H01L2224/05664 ,  H01L2924/01029 ,  H01L2924/01074 ,  H01L2924/01007 ,  H01L2224/03 ,  H01L2924/00 ,  H01L2224/05552

Abstract: A semiconductor device has a plurality of conductive vias formed into a semiconductor wafer. A portion of the semiconductor wafer is removed so the conductive vias extend above a surface of the semiconductor wafer. A notch is formed in the semiconductor wafer around each of the conductive vias. The notch around the conductive vias can be formed by wet etching, dry etching, or LDA. A first insulating layer is formed over a surface of the semiconductor wafer and conductive vias and into the notch to provide stress relief between the conductive vias and semiconductor wafer. A portion of the first insulating layer is removed to expose the conductive vias. A first conductive layer and second insulating layer can be formed around the conductive vias. A second conductive layer can be formed over the conductive vias. The notch can extend into the second insulating layer.

Abstract translation: 半导体器件具有形成为半导体晶片的多个导电通孔。 去除半导体晶片的一部分，使得导电通孔延伸到半导体晶片的表面之上。 在每个导电通孔周围的半导体晶片中形成切口。 导电通孔周围的凹口可以通过湿蚀刻，干蚀刻或LDA形成。 第一绝缘层形成在半导体晶片和导电通孔的表面上并进入凹口中，以在导电通孔和半导体晶片之间提供应力消除。 去除第一绝缘层的一部分以露出导电通孔。 可以在导电通孔周围形成第一导电层和第二绝缘层。 可以在导电通孔上形成第二导电层。 凹口可以延伸到第二绝缘层中。