公开(公告)号：US09837336B2

公开(公告)日：2017-12-05

申请号：US14257850

申请日：2014-04-21

Applicant: STATS ChipPAC, Ltd.

Inventor： Won Kyoung Choi ,  Chang Bum Yong ,  Jae Hun Ku

IPC: H01L23/48 ,  H01L23/31 ,  H01L21/683 ,  H01L25/065 ,  H01L21/768 ,  H01L23/00

CPC classification number: H01L23/481 ,  H01L21/6836 ,  H01L21/768 ,  H01L21/76898 ,  H01L23/3178 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L25/0657 ,  H01L2221/6834 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/05578 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/05669 ,  H01L2224/05671 ,  H01L2224/05681 ,  H01L2224/05684 ,  H01L2224/05686 ,  H01L2224/06181 ,  H01L2224/11334 ,  H01L2224/1146 ,  H01L2224/11849 ,  H01L2224/13025 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16146 ,  H01L2224/73104 ,  H01L2224/73204 ,  H01L2224/81005 ,  H01L2224/81191 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/01322 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/13091 ,  H01L2224/11 ,  H01L2924/01082 ,  H01L2924/04953 ,  H01L2924/01023 ,  H01L2224/05664 ,  H01L2924/01029 ,  H01L2924/01074 ,  H01L2924/01007 ,  H01L2224/03 ,  H01L2924/00 ,  H01L2224/05552

Abstract: A semiconductor device has a plurality of conductive vias formed into a semiconductor wafer. A portion of the semiconductor wafer is removed so the conductive vias extend above a surface of the semiconductor wafer. A notch is formed in the semiconductor wafer around each of the conductive vias. The notch around the conductive vias can be formed by wet etching, dry etching, or LDA. A first insulating layer is formed over a surface of the semiconductor wafer and conductive vias and into the notch to provide stress relief between the conductive vias and semiconductor wafer. A portion of the first insulating layer is removed to expose the conductive vias. A first conductive layer and second insulating layer can be formed around the conductive vias. A second conductive layer can be formed over the conductive vias. The notch can extend into the second insulating layer.

公开(公告)号：US20140264851A1

公开(公告)日：2014-09-18

申请号：US14288589

申请日：2014-05-28

Applicant: STATS ChipPAC, Ltd.

Inventor： Won Kyoung Choi ,  Chang Beom Yong ,  Jae Hun Ku

IPC: H01L25/065 ,  H01L23/00

CPC classification number: H01L25/0657 ,  H01L21/6836 ,  H01L21/76898 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L2221/6834 ,  H01L2224/0401 ,  H01L2224/05572 ,  H01L2224/05647 ,  H01L2224/11002 ,  H01L2224/1145 ,  H01L2224/1146 ,  H01L2224/11849 ,  H01L2224/11901 ,  H01L2224/13025 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/1403 ,  H01L2224/14131 ,  H01L2224/14181 ,  H01L2224/16148 ,  H01L2224/48091 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/94 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/01322 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/351 ,  H01L2224/11 ,  H01L2924/00012 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/00 ,  H01L2224/05552

Abstract: A semiconductor device has a plurality of conductive vias formed through the semiconductor die with a first insulating layer around the conductive vias. A recess is formed in the first insulating layer around the conductive vias by LDA. A portion of the semiconductor wafer is removed by LDA after forming the recess in the first insulating layer so that the conductive vias extend above a surface of the semiconductor wafer. The first insulating layer extends to the surface of the semiconductor wafer or above the surface of the semiconductor wafer. A second insulating layer is formed over the surface of the semiconductor wafer and conductive vias. A first portion of the second insulating layer is removed by LDA, while leaving a second portion of the second insulating layer over the surface of the semiconductor wafer around the conductive vias. An electroless plated bump is formed over the conductive vias.

Abstract translation: 半导体器件具有通过半导体管芯形成的多个导电通孔，其具有围绕导电通孔的第一绝缘层。 在LDA的导电通孔周围的第一绝缘层中形成凹部。 在第一绝缘层中形成凹陷之后，半导体晶片的一部分被LDA去除，使得导电通孔延伸到半导体晶片的表面之上。 第一绝缘层延伸到半导体晶片的表面或半导体晶片的表面之上。 第二绝缘层形成在半导体晶片的表面和导电通孔上。 第二绝缘层的第一部分被LDA去除，同时在第二绝缘层的第二部分围绕导电通孔留在半导体晶片的表面上。 在导电通孔上形成无电镀凸块。

公开(公告)号：US20140225279A1

公开(公告)日：2014-08-14

申请号：US14257850

申请日：2014-04-21

Applicant: STATS ChipPAC, Ltd.

Inventor： Won Kyoung Choi ,  Chang Bum Yong ,  Jae Hun Ku

IPC: H01L23/48 ,  H01L21/768

CPC classification number: H01L23/481 ,  H01L21/6836 ,  H01L21/768 ,  H01L21/76898 ,  H01L23/3178 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L25/0657 ,  H01L2221/6834 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/05578 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/05669 ,  H01L2224/05671 ,  H01L2224/05681 ,  H01L2224/05684 ,  H01L2224/05686 ,  H01L2224/06181 ,  H01L2224/11334 ,  H01L2224/1146 ,  H01L2224/11849 ,  H01L2224/13025 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16146 ,  H01L2224/73104 ,  H01L2224/73204 ,  H01L2224/81005 ,  H01L2224/81191 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/01322 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/13091 ,  H01L2224/11 ,  H01L2924/01082 ,  H01L2924/04953 ,  H01L2924/01023 ,  H01L2224/05664 ,  H01L2924/01029 ,  H01L2924/01074 ,  H01L2924/01007 ,  H01L2224/03 ,  H01L2924/00 ,  H01L2224/05552

Abstract: A semiconductor device has a plurality of conductive vias formed into a semiconductor wafer. A portion of the semiconductor wafer is removed so the conductive vias extend above a surface of the semiconductor wafer. A notch is formed in the semiconductor wafer around each of the conductive vias. The notch around the conductive vias can be formed by wet etching, dry etching, or LDA. A first insulating layer is formed over a surface of the semiconductor wafer and conductive vias and into the notch to provide stress relief between the conductive vias and semiconductor wafer. A portion of the first insulating layer is removed to expose the conductive vias. A first conductive layer and second insulating layer can be formed around the conductive vias. A second conductive layer can be formed over the conductive vias. The notch can extend into the second insulating layer.

Abstract translation: 半导体器件具有形成为半导体晶片的多个导电通孔。 去除半导体晶片的一部分，使得导电通孔延伸到半导体晶片的表面之上。 在每个导电通孔周围的半导体晶片中形成切口。 导电通孔周围的凹口可以通过湿蚀刻，干蚀刻或LDA形成。 第一绝缘层形成在半导体晶片和导电通孔的表面上并进入凹口中，以在导电通孔和半导体晶片之间提供应力消除。 去除第一绝缘层的一部分以露出导电通孔。 可以在导电通孔周围形成第一导电层和第二绝缘层。 可以在导电通孔上形成第二导电层。 凹口可以延伸到第二绝缘层中。

公开(公告)号：US09601462B2

公开(公告)日：2017-03-21

申请号：US14288589

申请日：2014-05-28

Applicant: STATS ChipPAC, Ltd.

Inventor： Won Kyoung Choi ,  Chang Beom Yong ,  Jae Hun Ku

IPC: H01L25/00 ,  H01L25/065 ,  H01L21/768 ,  H01L23/00 ,  H01L21/683

CPC classification number: H01L25/0657 ,  H01L21/6836 ,  H01L21/76898 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L2221/6834 ,  H01L2224/0401 ,  H01L2224/05572 ,  H01L2224/05647 ,  H01L2224/11002 ,  H01L2224/1145 ,  H01L2224/1146 ,  H01L2224/11849 ,  H01L2224/11901 ,  H01L2224/13025 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/1403 ,  H01L2224/14131 ,  H01L2224/14181 ,  H01L2224/16148 ,  H01L2224/48091 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/94 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/01322 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/351 ,  H01L2224/11 ,  H01L2924/00012 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/00 ,  H01L2224/05552

Abstract: A semiconductor device has a plurality of conductive vias formed through the semiconductor die with a first insulating layer around the conductive vias. A recess is formed in the first insulating layer around the conductive vias by LDA. A portion of the semiconductor wafer is removed by LDA after forming the recess in the first insulating layer so that the conductive vias extend above a surface of the semiconductor wafer. The first insulating layer extends to the surface of the semiconductor wafer or above the surface of the semiconductor wafer. A second insulating layer is formed over the surface of the semiconductor wafer and conductive vias. A first portion of the second insulating layer is removed by LDA, while leaving a second portion of the second insulating layer over the surface of the semiconductor wafer around the conductive vias. An electroless plated bump is formed over the conductive vias.

公开(公告)号：US09054083B2

公开(公告)日：2015-06-09

申请号：US14143891

申请日：2013-12-30

Applicant: STATS ChipPAC, Ltd.

Inventor： Nathapong Suthiwongsunthorn ,  Pandi C. Marimuthu ,  Jae Hun Ku ,  Glenn Omandam ,  Hin Hwa Goh ,  Kock Liang Heng ,  Jose A. Caparas

IPC: H01L21/311 ,  H01L21/48 ,  H01L21/56 ,  H01L21/768 ,  H01L23/31 ,  H01L23/48 ,  H01L23/00 ,  H01L23/498

CPC classification number: H01L21/486 ,  H01L21/561 ,  H01L21/563 ,  H01L21/76898 ,  H01L23/3128 ,  H01L23/481 ,  H01L23/49827 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/48 ,  H01L24/92 ,  H01L24/94 ,  H01L24/95 ,  H01L2224/0401 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/1134 ,  H01L2224/13022 ,  H01L2224/13025 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/29111 ,  H01L2224/2919 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2224/83805 ,  H01L2224/85399 ,  H01L2224/94 ,  H01L2924/0001 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/09701 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15174 ,  H01L2924/15184 ,  H01L2924/15311 ,  H01L2924/1579 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/30105 ,  H01L2224/03 ,  H01L2224/11 ,  H01L2924/00 ,  H01L2924/0665 ,  H01L2224/81 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor device includes a substrate and a via extending through the substrate. A first insulating layer is disposed on sidewalls of the via. An electrically conductive material is disposed in the via over the first insulating layer to form a TSV. A first interconnect structure is disposed over a first side of the substrate. A semiconductor die or a component is mounted to the first interconnect structure. An encapsulant is disposed over the first interconnect structure and semiconductor die or component. A second interconnect structure is disposed over the second side of the substrate. The second interconnect structure is electrically connected to the TSV. The second interconnect structure includes a second insulating layer disposed over the second surface of the substrate and TSV, and a first conductive layer disposed over the TSV and in contact with the TSV through the second insulating layer.

Abstract translation: 半导体器件包括衬底和延伸通过衬底的通孔。 第一绝缘层设置在通孔的侧壁上。 在第一绝缘层上的通孔中设置导电材料以形成TSV。 第一互连结构设置在衬底的第一侧上。 半导体管芯或部件安装到第一互连结构。 密封剂设置在第一互连结构和半导体管芯或部件上。 第二互连结构设置在衬底的第二侧上。 第二互连结构电连接到TSV。 第二互连结构包括设置在衬底的第二表面上的第二绝缘层和TSV，以及设置在TSV上方并通过第二绝缘层与TSV接触的第一导电层。

公开(公告)号：US20140110861A1

公开(公告)日：2014-04-24

申请号：US14143891

申请日：2013-12-30

Applicant: STATS ChipPAC, Ltd

Inventor： Nathapong Suthiwongsunthorn ,  Pandi C. Marimuthu ,  Jae Hun Ku ,  Glenn Omandam ,  Hin Hwa Goh ,  Kock Liang Heng ,  Jose A. Caparas

IPC: H01L21/48 ,  H01L23/498 ,  H01L21/56

CPC classification number: H01L21/486 ,  H01L21/561 ,  H01L21/563 ,  H01L21/76898 ,  H01L23/3128 ,  H01L23/481 ,  H01L23/49827 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/48 ,  H01L24/92 ,  H01L24/94 ,  H01L24/95 ,  H01L2224/0401 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/1134 ,  H01L2224/13022 ,  H01L2224/13025 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/29111 ,  H01L2224/2919 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2224/83805 ,  H01L2224/85399 ,  H01L2224/94 ,  H01L2924/0001 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/09701 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15174 ,  H01L2924/15184 ,  H01L2924/15311 ,  H01L2924/1579 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/30105 ,  H01L2224/03 ,  H01L2224/11 ,  H01L2924/00 ,  H01L2924/0665 ,  H01L2224/81 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor device includes a substrate and a via extending through the substrate. A first insulating layer is disposed on sidewalls of the via. An electrically conductive material is disposed in the via over the first insulating layer to form a TSV. A first interconnect structure is disposed over a first side of the substrate. A semiconductor die or a component is mounted to the first interconnect structure. An encapsulant is disposed over the first interconnect structure and semiconductor die or component. A second interconnect structure is disposed over the second side of the substrate. The second interconnect structure is electrically connected to the TSV. The second interconnect structure includes a second insulating layer disposed over the second surface of the substrate and TSV, and a first conductive layer disposed over the TSV and in contact with the TSV through the second insulating layer.

Abstract translation: 半导体器件包括衬底和延伸穿过衬底的通孔。 第一绝缘层设置在通孔的侧壁上。 在第一绝缘层上的通孔中设置导电材料以形成TSV。 第一互连结构设置在衬底的第一侧上。 半导体管芯或部件安装到第一互连结构。 密封剂设置在第一互连结构和半导体管芯或部件上。 第二互连结构设置在衬底的第二侧上。 第二互连结构电连接到TSV。 第二互连结构包括设置在衬底的第二表面上的第二绝缘层和TSV，以及设置在TSV上方并通过第二绝缘层与TSV接触的第一导电层。