公开(公告)号：US09865524B2

公开(公告)日：2018-01-09

申请号：US14222547

申请日：2014-03-21

Applicant: STATS ChipPAC, Ltd.

Inventor： Duk Ju Na ,  Chang Beom Yong ,  Pandi C. Marimuthu

IPC: H01L23/48 ,  H01L23/00 ,  H01L21/768 ,  H01L23/31 ,  H01L21/66

CPC classification number: H01L23/481 ,  H01L21/76898 ,  H01L22/12 ,  H01L22/14 ,  H01L23/3171 ,  H01L23/3192 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/94 ,  H01L2224/03002 ,  H01L2224/03009 ,  H01L2224/0345 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/0401 ,  H01L2224/05009 ,  H01L2224/05027 ,  H01L2224/05558 ,  H01L2224/0557 ,  H01L2224/0558 ,  H01L2224/05584 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/05666 ,  H01L2224/05669 ,  H01L2224/05671 ,  H01L2224/05684 ,  H01L2224/06181 ,  H01L2224/11002 ,  H01L2224/11009 ,  H01L2224/1132 ,  H01L2224/11334 ,  H01L2224/1145 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/11849 ,  H01L2224/11901 ,  H01L2224/13022 ,  H01L2224/13025 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/14181 ,  H01L2224/94 ,  H01L2924/00014 ,  H01L2924/01322 ,  H01L2924/10252 ,  H01L2924/10253 ,  H01L2924/10272 ,  H01L2924/10322 ,  H01L2924/10324 ,  H01L2924/10329 ,  H01L2924/1033 ,  H01L2924/10335 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/1433 ,  H01L2924/14335 ,  H01L2924/1434 ,  H01L2924/181 ,  H01L2224/03 ,  H01L2224/11 ,  H01L2924/01023 ,  H01L2924/01074 ,  H01L2924/01029 ,  H01L2924/00 ,  H01L2224/05552

Abstract: A semiconductor device includes a plurality of semiconductor die and a plurality of conductive vias formed in the semiconductor die. An insulating layer is formed over the semiconductor die while leaving the conductive vias exposed. An interconnect structure is formed over the insulating layer and conductive vias. The insulating layer is formed using electrografting or oxidation. An under bump metallization is formed over the conductive vias. A portion of the semiconductor die is removed to expose the conductive vias. The interconnect structure is formed over two or more of the conductive vias. A portion of the semiconductor die is removed to leave the conductive vias with a height greater than a height of the semiconductor die. A second insulating layer is formed over the first insulating layer. A portion of the second insulating layer is removed to expose the conductive via.

公开(公告)号：US20140300002A1

公开(公告)日：2014-10-09

申请号：US14222547

申请日：2014-03-21

Applicant: STATS ChipPAC, Ltd.

Inventor： Duk Ju Na ,  Chang Beom Yong ,  Pandi C. Marimuthu

IPC: H01L23/48 ,  H01L23/00

CPC classification number: H01L23/481 ,  H01L21/76898 ,  H01L22/12 ,  H01L22/14 ,  H01L23/3171 ,  H01L23/3192 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/94 ,  H01L2224/03002 ,  H01L2224/03009 ,  H01L2224/0345 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/0401 ,  H01L2224/05009 ,  H01L2224/05027 ,  H01L2224/05558 ,  H01L2224/0557 ,  H01L2224/0558 ,  H01L2224/05584 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/05666 ,  H01L2224/05669 ,  H01L2224/05671 ,  H01L2224/05684 ,  H01L2224/06181 ,  H01L2224/11002 ,  H01L2224/11009 ,  H01L2224/1132 ,  H01L2224/11334 ,  H01L2224/1145 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/11849 ,  H01L2224/11901 ,  H01L2224/13022 ,  H01L2224/13025 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/14181 ,  H01L2224/94 ,  H01L2924/00014 ,  H01L2924/01322 ,  H01L2924/10252 ,  H01L2924/10253 ,  H01L2924/10272 ,  H01L2924/10322 ,  H01L2924/10324 ,  H01L2924/10329 ,  H01L2924/1033 ,  H01L2924/10335 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/1433 ,  H01L2924/14335 ,  H01L2924/1434 ,  H01L2924/181 ,  H01L2224/03 ,  H01L2224/11 ,  H01L2924/01023 ,  H01L2924/01074 ,  H01L2924/01029 ,  H01L2924/00 ,  H01L2224/05552

Abstract: A semiconductor device includes a plurality of semiconductor die and a plurality of conductive vias formed in the semiconductor die. An insulating layer is formed over the semiconductor die while leaving the conductive vias exposed. An interconnect structure is formed over the insulating layer and conductive vias. The insulating layer is formed using electrografting or oxidation. An under bump metallization is formed over the conductive vias. A portion of the semiconductor die is removed to expose the conductive vias. The interconnect structure is formed over two or more of the conductive vias. A portion of the semiconductor die is removed to leave the conductive vias with a height greater than a height of the semiconductor die. A second insulating layer is formed over the first insulating layer. A portion of the second insulating layer is removed to expose the conductive via.

Abstract translation: 半导体器件包括多个半导体管芯和形成在半导体管芯中的多个导电通孔。 在半导体管芯上形成绝缘层，同时使导电通孔露出。 在绝缘层和导电通孔上形成互连结构。 绝缘层使用电动或氧化形成。 在导电通孔上形成凸块下金属化。 去除半导体管芯的一部分以露出导电通孔。 互连结构形成在两个或更多个导电通孔上。 去除半导体管芯的一部分以留下具有大于半导体管芯高度的高度的导电通孔。 在第一绝缘层上形成第二绝缘层。 去除第二绝缘层的一部分以露出导电通孔。

公开(公告)号：US20130299998A1

公开(公告)日：2013-11-14

申请号：US13939044

申请日：2013-07-10

Applicant: STATS ChipPAC, Ltd.

Inventor： Duk Ju Na ,  Lai Yee Chia ,  Chang Beom Yong

IPC: H01L23/498 ,  H01L21/768

CPC classification number: H01L23/49827 ,  H01L21/561 ,  H01L21/568 ,  H01L21/6836 ,  H01L21/76801 ,  H01L21/76898 ,  H01L23/481 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/94 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2224/02166 ,  H01L2224/0345 ,  H01L2224/0346 ,  H01L2224/0391 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05015 ,  H01L2224/05555 ,  H01L2224/05567 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05666 ,  H01L2224/05681 ,  H01L2224/06181 ,  H01L2224/1132 ,  H01L2224/11334 ,  H01L2224/1145 ,  H01L2224/1146 ,  H01L2224/11849 ,  H01L2224/13025 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/27002 ,  H01L2224/27005 ,  H01L2224/27312 ,  H01L2224/2919 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73104 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/94 ,  H01L2924/00011 ,  H01L2924/01322 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2224/11 ,  H01L2924/00014 ,  H01L2224/27 ,  H01L2924/00012 ,  H01L2224/03 ,  H01L2924/01074 ,  H01L2924/01029 ,  H01L2924/01007 ,  H01L2924/0665 ,  H01L2224/81805

Abstract: A semiconductor device has a plurality of conductive vias formed into a semiconductor wafer. An insulating lining is formed around the conductive vias and a conductive layer is formed over the insulating lining. A portion of the semiconductor wafer is removed so the conductive vias extend above a surface of the semiconductor wafer. A first insulating layer is formed over the surface of the semiconductor wafer and conductive vias. A first portion of the first insulating layer is removed and a second portion of the first insulating layer remains as guard rings around the conductive vias. A conductive layer is formed over the conductive vias. A second insulating layer is formed over the surface of the semiconductor wafer, guard rings, and conductive vias. A portion of the second insulating layer is removed to expose the conductive vias and a portion of the guard rings.

Abstract translation: 半导体器件具有形成为半导体晶片的多个导电通孔。 在导电通孔周围形成绝缘衬里，并且在绝缘衬里上形成导电层。 去除半导体晶片的一部分，使得导电通孔延伸到半导体晶片的表面之上。 在半导体晶片和导电通孔的表面上形成第一绝缘层。 去除第一绝缘层的第一部分，并且第一绝缘层的第二部分保持围绕导电通孔的保护环。 在导电通孔上形成导电层。 在半导体晶片的表面上形成第二绝缘层，保护环和导电通孔。 去除第二绝缘层的一部分以露出导电通孔和保护环的一部分。

公开(公告)号：US09601462B2

公开(公告)日：2017-03-21

申请号：US14288589

申请日：2014-05-28

Applicant: STATS ChipPAC, Ltd.

Inventor： Won Kyoung Choi ,  Chang Beom Yong ,  Jae Hun Ku

IPC: H01L25/00 ,  H01L25/065 ,  H01L21/768 ,  H01L23/00 ,  H01L21/683

CPC classification number: H01L25/0657 ,  H01L21/6836 ,  H01L21/76898 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L2221/6834 ,  H01L2224/0401 ,  H01L2224/05572 ,  H01L2224/05647 ,  H01L2224/11002 ,  H01L2224/1145 ,  H01L2224/1146 ,  H01L2224/11849 ,  H01L2224/11901 ,  H01L2224/13025 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/1403 ,  H01L2224/14131 ,  H01L2224/14181 ,  H01L2224/16148 ,  H01L2224/48091 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/94 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/01322 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/351 ,  H01L2224/11 ,  H01L2924/00012 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/00 ,  H01L2224/05552

Abstract: A semiconductor device has a plurality of conductive vias formed through the semiconductor die with a first insulating layer around the conductive vias. A recess is formed in the first insulating layer around the conductive vias by LDA. A portion of the semiconductor wafer is removed by LDA after forming the recess in the first insulating layer so that the conductive vias extend above a surface of the semiconductor wafer. The first insulating layer extends to the surface of the semiconductor wafer or above the surface of the semiconductor wafer. A second insulating layer is formed over the surface of the semiconductor wafer and conductive vias. A first portion of the second insulating layer is removed by LDA, while leaving a second portion of the second insulating layer over the surface of the semiconductor wafer around the conductive vias. An electroless plated bump is formed over the conductive vias.

公开(公告)号：US09076655B2

公开(公告)日：2015-07-07

申请号：US13743054

申请日：2013-01-16

Applicant: STATS ChipPAC, Ltd.

Inventor： Duk Ju Na ,  Calvert Tan ,  Chang Beom Yong

IPC: H01L21/44 ,  H01L21/02

CPC classification number: H01L21/02697 ,  H01L21/568 ,  H01L21/6835 ,  H01L21/76898 ,  H01L23/3171 ,  H01L23/552 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L24/92 ,  H01L25/0657 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2224/03002 ,  H01L2224/0332 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/0401 ,  H01L2224/05009 ,  H01L2224/0557 ,  H01L2224/05666 ,  H01L2224/05687 ,  H01L2224/06181 ,  H01L2224/1132 ,  H01L2224/11334 ,  H01L2224/1134 ,  H01L2224/1145 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/11849 ,  H01L2224/11901 ,  H01L2224/13025 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/73104 ,  H01L2224/73204 ,  H01L2224/92 ,  H01L2224/9202 ,  H01L2224/92125 ,  H01L2224/92222 ,  H01L2224/92242 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/3025 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2924/01082 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01047 ,  H01L2924/04941 ,  H01L2924/00012 ,  H01L2224/03 ,  H01L2224/11 ,  H01L2221/68304 ,  H01L2224/27 ,  H01L2221/68372 ,  H01L21/56 ,  H01L2221/68381 ,  H01L21/563 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2924/00

Abstract: A semiconductor device can be formed by first providing a semiconductor wafer, and forming a conductive via into the semiconductor wafer. A portion of the semiconductor wafer can be removed so that the conductive via extends above a surface of the semiconductor wafer. A first insulating layer can be formed over the surface of the semiconductor wafer and the conductive via, followed by a second insulating layer, the second insulating layer having a different material composition than the first insulating layer. Portions of the insulating layers can be removed to expose the conductive via.

Abstract translation: 可以通过首先提供半导体晶片并在半导体晶片中形成导电通孔来形成半导体器件。 可以去除半导体晶片的一部分，使得导电通孔延伸到半导体晶片的表面之上。 可以在半导体晶片和导电通孔的表面上形成第一绝缘层，随后是第二绝缘层，第二绝缘层具有与第一绝缘层不同的材料组成。 可以去除部分绝缘层以露出导电通孔。

公开(公告)号：US09257382B2

公开(公告)日：2016-02-09

申请号：US13939044

申请日：2013-07-10

Applicant: STATS ChipPAC, Ltd.

Inventor： Duk Ju Na ,  Lai Yee Chia ,  Chang Beom Yong

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L23/498 ,  H01L21/768 ,  H01L21/56 ,  H01L21/683 ,  H01L23/00

CPC classification number: H01L23/49827 ,  H01L21/561 ,  H01L21/568 ,  H01L21/6836 ,  H01L21/76801 ,  H01L21/76898 ,  H01L23/481 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/94 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2224/02166 ,  H01L2224/0345 ,  H01L2224/0346 ,  H01L2224/0391 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05015 ,  H01L2224/05555 ,  H01L2224/05567 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05666 ,  H01L2224/05681 ,  H01L2224/06181 ,  H01L2224/1132 ,  H01L2224/11334 ,  H01L2224/1145 ,  H01L2224/1146 ,  H01L2224/11849 ,  H01L2224/13025 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/27002 ,  H01L2224/27005 ,  H01L2224/27312 ,  H01L2224/2919 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73104 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/94 ,  H01L2924/00011 ,  H01L2924/01322 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2224/11 ,  H01L2924/00014 ,  H01L2224/27 ,  H01L2924/00012 ,  H01L2224/03 ,  H01L2924/01074 ,  H01L2924/01029 ,  H01L2924/01007 ,  H01L2924/0665 ,  H01L2224/81805

Abstract: A semiconductor device has a plurality of conductive vias formed into a semiconductor wafer. An insulating lining is formed around the conductive vias and a conductive layer is formed over the insulating lining. A portion of the semiconductor wafer is removed so the conductive vias extend above a surface of the semiconductor wafer. A first insulating layer is formed over the surface of the semiconductor wafer and conductive vias. A first portion of the first insulating layer is removed and a second portion of the first insulating layer remains as guard rings around the conductive vias. A conductive layer is formed over the conductive vias. A second insulating layer is formed over the surface of the semiconductor wafer, guard rings, and conductive vias. A portion of the second insulating layer is removed to expose the conductive vias and a portion of the guard rings.

公开(公告)号：US20140264851A1

公开(公告)日：2014-09-18

申请号：US14288589

申请日：2014-05-28

Applicant: STATS ChipPAC, Ltd.

Inventor： Won Kyoung Choi ,  Chang Beom Yong ,  Jae Hun Ku

IPC: H01L25/065 ,  H01L23/00

CPC classification number: H01L25/0657 ,  H01L21/6836 ,  H01L21/76898 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L2221/6834 ,  H01L2224/0401 ,  H01L2224/05572 ,  H01L2224/05647 ,  H01L2224/11002 ,  H01L2224/1145 ,  H01L2224/1146 ,  H01L2224/11849 ,  H01L2224/11901 ,  H01L2224/13025 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/1403 ,  H01L2224/14131 ,  H01L2224/14181 ,  H01L2224/16148 ,  H01L2224/48091 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/94 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/01322 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/351 ,  H01L2224/11 ,  H01L2924/00012 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/00 ,  H01L2224/05552

Abstract: A semiconductor device has a plurality of conductive vias formed through the semiconductor die with a first insulating layer around the conductive vias. A recess is formed in the first insulating layer around the conductive vias by LDA. A portion of the semiconductor wafer is removed by LDA after forming the recess in the first insulating layer so that the conductive vias extend above a surface of the semiconductor wafer. The first insulating layer extends to the surface of the semiconductor wafer or above the surface of the semiconductor wafer. A second insulating layer is formed over the surface of the semiconductor wafer and conductive vias. A first portion of the second insulating layer is removed by LDA, while leaving a second portion of the second insulating layer over the surface of the semiconductor wafer around the conductive vias. An electroless plated bump is formed over the conductive vias.

Abstract translation: 半导体器件具有通过半导体管芯形成的多个导电通孔，其具有围绕导电通孔的第一绝缘层。 在LDA的导电通孔周围的第一绝缘层中形成凹部。 在第一绝缘层中形成凹陷之后，半导体晶片的一部分被LDA去除，使得导电通孔延伸到半导体晶片的表面之上。 第一绝缘层延伸到半导体晶片的表面或半导体晶片的表面之上。 第二绝缘层形成在半导体晶片的表面和导电通孔上。 第二绝缘层的第一部分被LDA去除，同时在第二绝缘层的第二部分围绕导电通孔留在半导体晶片的表面上。 在导电通孔上形成无电镀凸块。

公开(公告)号：US20140199838A1

公开(公告)日：2014-07-17

申请号：US13743054

申请日：2013-01-16

Applicant: STATS CHIPPAC, LTD.

Inventor： Duk Ju Na ,  Calvert Tan ,  Chang Beom Yong

IPC: H01L21/02

CPC classification number: H01L21/02697 ,  H01L21/568 ,  H01L21/6835 ,  H01L21/76898 ,  H01L23/3171 ,  H01L23/552 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L24/92 ,  H01L25/0657 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2224/03002 ,  H01L2224/0332 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/0401 ,  H01L2224/05009 ,  H01L2224/0557 ,  H01L2224/05666 ,  H01L2224/05687 ,  H01L2224/06181 ,  H01L2224/1132 ,  H01L2224/11334 ,  H01L2224/1134 ,  H01L2224/1145 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/11849 ,  H01L2224/11901 ,  H01L2224/13025 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/73104 ,  H01L2224/73204 ,  H01L2224/92 ,  H01L2224/9202 ,  H01L2224/92125 ,  H01L2224/92222 ,  H01L2224/92242 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/3025 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2924/01082 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01047 ,  H01L2924/04941 ,  H01L2924/00012 ,  H01L2224/03 ,  H01L2224/11 ,  H01L2221/68304 ,  H01L2224/27 ,  H01L2221/68372 ,  H01L21/56 ,  H01L2221/68381 ,  H01L21/563 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2924/00

Abstract: A semiconductor device can be formed by first providing a semiconductor wafer, and forming a conductive via into the semiconductor wafer. A portion of the semiconductor wafer can be removed so that the conductive via extends above a surface of the semiconductor wafer. A first insulating layer can be formed over the surface of the semiconductor wafer and the conductive via, followed by a second insulating layer, the second insulating layer having a different material composition than the first insulating layer. Portions of the insulating layers can be removed to expose the conductive via.

Abstract translation: 可以通过首先提供半导体晶片并在半导体晶片中形成导电通孔来形成半导体器件。 可以去除半导体晶片的一部分，使得导电通孔延伸到半导体晶片的表面之上。 可以在半导体晶片和导电通孔的表面上形成第一绝缘层，随后是第二绝缘层，第二绝缘层具有与第一绝缘层不同的材料组成。 可以去除部分绝缘层以露出导电通孔。