Invention Application
- Patent Title: Semiconductor Device and Method of Forming Conductive Vias Using Backside Via Reveal and Selective Passivation
- Patent Title (中): 半导体器件和使用背面透视和选择性钝化形成导电通孔的方法
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Application No.: US14222547Application Date: 2014-03-21
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Publication No.: US20140300002A1Publication Date: 2014-10-09
- Inventor: Duk Ju Na , Chang Beom Yong , Pandi C. Marimuthu
- Applicant: STATS ChipPAC, Ltd.
- Applicant Address: SG Singapore
- Assignee: STATS ChipPAC, Ltd.
- Current Assignee: STATS ChipPAC, Ltd.
- Current Assignee Address: SG Singapore
- Main IPC: H01L23/48
- IPC: H01L23/48 ; H01L23/00

Abstract:
A semiconductor device includes a plurality of semiconductor die and a plurality of conductive vias formed in the semiconductor die. An insulating layer is formed over the semiconductor die while leaving the conductive vias exposed. An interconnect structure is formed over the insulating layer and conductive vias. The insulating layer is formed using electrografting or oxidation. An under bump metallization is formed over the conductive vias. A portion of the semiconductor die is removed to expose the conductive vias. The interconnect structure is formed over two or more of the conductive vias. A portion of the semiconductor die is removed to leave the conductive vias with a height greater than a height of the semiconductor die. A second insulating layer is formed over the first insulating layer. A portion of the second insulating layer is removed to expose the conductive via.
Public/Granted literature
Information query
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