公开(公告)号：US20150380339A1

公开(公告)日：2015-12-31

申请号：US14316561

申请日：2014-06-26

Applicant: STATS ChipPAC, Ltd.

Inventor： Xing Zhao ,  Duk Ju Na ,  Siew Joo Tan ,  Pandi C. Marimuthu

IPC: H01L23/48 ,  H01L21/306 ,  H01L25/065 ,  H01L21/78 ,  H01L25/00 ,  H01L21/768 ,  H01L21/3105

CPC classification number: H01L25/0657 ,  H01L21/76898 ,  H01L21/78 ,  H01L23/291 ,  H01L23/293 ,  H01L23/3192 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L24/81 ,  H01L24/94 ,  H01L25/50 ,  H01L2224/03002 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/0346 ,  H01L2224/03602 ,  H01L2224/03616 ,  H01L2224/0391 ,  H01L2224/0401 ,  H01L2224/05111 ,  H01L2224/05124 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05184 ,  H01L2224/05562 ,  H01L2224/05568 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/05681 ,  H01L2224/05684 ,  H01L2224/06181 ,  H01L2224/1132 ,  H01L2224/11334 ,  H01L2224/1145 ,  H01L2224/11849 ,  H01L2224/13023 ,  H01L2224/13025 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16013 ,  H01L2224/16014 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/81191 ,  H01L2224/81815 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2924/13091 ,  H01L2224/03 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/01074 ,  H01L2924/01029 ,  H01L2924/01007 ,  H01L2924/01082

Abstract: A semiconductor device has a semiconductor wafer and a conductive via formed through the semiconductor wafer. A portion of the semiconductor wafer is removed such that a portion of the conductive via extends above the semiconductor wafer. A first insulating layer is formed over the conductive via and semiconductor wafer. A second insulating layer is formed over the first insulating layer. The first insulating layer includes an inorganic material and the second insulating layer includes an organic material. A portion of the first and second insulating layers is removed simultaneously from over the conductive via by chemical mechanical polishing (CMP). Alternatively, a first insulating layer including an organic material is formed over the conductive via and semiconductor wafer. A portion of the first insulating layer is removed by CMP. A conductive layer is formed over the conductive via and first insulating layer. The conductive layer is substantially planar.

Abstract translation: 半导体器件具有通过半导体晶片形成的半导体晶片和导电通孔。 去除半导体晶片的一部分，使得导电通孔的一部分延伸到半导体晶片之上。 在导电通孔和半导体晶片之上形成第一绝缘层。 在第一绝缘层上形成第二绝缘层。 第一绝缘层包括无机材料，第二绝缘层包括有机材料。 通过化学机械抛光（CMP），第一和第二绝缘层的一部分被同时从导电通孔上除去。 或者，在导电通孔和半导体晶片之上形成包括有机材料的第一绝缘层。 通过CMP去除第一绝缘层的一部分。 导电层形成在导电通孔和第一绝缘层之上。 导电层基本上是平面的。

公开(公告)号：US10115701B2

公开(公告)日：2018-10-30

申请号：US14316561

申请日：2014-06-26

Applicant: STATS ChipPAC, Ltd.

Inventor： Xing Zhao ,  Duk Ju Na ,  Siew Joo Tan ,  Pandi C. Marimuthu

IPC: H01L25/065 ,  H01L23/00 ,  H01L21/78 ,  H01L21/768 ,  H01L25/00

Abstract: A semiconductor device has a semiconductor wafer and a conductive via formed through the semiconductor wafer. A portion of the semiconductor wafer is removed such that a portion of the conductive via extends above the semiconductor wafer. A first insulating layer is formed over the conductive via and semiconductor wafer. A second insulating layer is formed over the first insulating layer. The first insulating layer includes an inorganic material and the second insulating layer includes an organic material. A portion of the first and second insulating layers is removed simultaneously from over the conductive via by chemical mechanical polishing (CMP). Alternatively, a first insulating layer including an organic material is formed over the conductive via and semiconductor wafer. A portion of the first insulating layer is removed by CMP. A conductive layer is formed over the conductive via and first insulating layer. The conductive layer is substantially planar.