公开(公告)号：US10411091B1

公开(公告)日：2019-09-10

申请号：US16034746

申请日：2018-07-13

Applicant: QUALCOMM Incorporated

Inventor： Mustafa Badaroglu ,  Kern Rim

IPC: H01L29/06 ,  H01L29/66 ,  H01L27/092 ,  H01L29/417 ,  H01L29/40 ,  H01L29/78

Abstract: Integrated circuits employing a field gate(s) without dielectric layers and/or work function metal layers for reduced gate layout parasitic resistance, and related methods are disclosed. At least a portion of the dielectric layers and/or work function metal layers present in active gate(s) is not present in a field gate(s) of a gate in a circuit cell. The field gate(s) have more conductive gate material than the active gate(s). In this manner, the increased volume of gate material in the field gate(s) reduces gate layout parasitic resistance. The active gate(s) retains the dielectric layers and/or work function metal layers to effectively isolate the gate material from a channel of a FET formed from the circuit cell to provide effective channel control. Reducing gate layout parasitic resistance can reduce current (I) resistance (R) (IR) drop to achieve the desired drive strength in the integrated circuit.

公开(公告)号：US20190067435A1

公开(公告)日：2019-02-28

申请号：US16171061

申请日：2018-10-25

Applicant: QUALCOMM Incorporated

Inventor： Mustafa Badaroglu ,  Vladimir Machkaoutsan ,  Stanley Seungchul Song ,  Jeffrey Junhao Xu ,  Matthew Michael Nowak ,  Choh Fei Yeap

IPC: H01L29/423 ,  H01L29/775 ,  B82Y10/00 ,  H01L29/06 ,  H01L29/66 ,  H01L29/08 ,  H01L29/165 ,  H01L29/49 ,  H01L21/762 ,  H01L21/02 ,  H01L29/78

Abstract: A nanowire transistor is provided that includes a well implant having a local isolation region for insulating a replacement metal gate from a parasitic channel. In addition, the nanowire transistor includes oxidized caps in the extension regions that inhibit parasitic gate-to-source and gate-to-drain capacitances.

公开(公告)号：US10090244B2

公开(公告)日：2018-10-02

申请号：US15634039

申请日：2017-06-27

Applicant: QUALCOMM Incorporated

Inventor： Jeffrey Junhao Xu ,  Mustafa Badaroglu ,  Da Yang ,  Periannan Chidambaram

IPC: H01L23/528 ,  H01L21/768 ,  H01L23/532 ,  H01L27/02 ,  G06F17/50 ,  H01L27/118

Abstract: Standard cell circuits employing high aspect ratio voltage rails for reduced resistance are disclosed. In one aspect, a standard cell circuit is provided that employs a first high aspect ratio voltage rail configured to receive a first supply voltage. A second high aspect ratio voltage rail is employed that is disposed substantially parallel to the first high aspect ratio voltage rail. A voltage differential between the first and second high aspect ratio voltage rails is used to power a circuit device in the standard cell circuit. The first and second high aspect ratio voltage rails each have a height-to-width ratio greater than 1.0. The height of each respective first and second high aspect ratio voltage rail is greater than each respective width. Employing the first and second high aspect ratio voltage rails allows each to have a cross-sectional area that limits the resistance and corresponding IR drop.

公开(公告)号：US20180212029A1

公开(公告)日：2018-07-26

申请号：US15874005

申请日：2018-01-18

Applicant: QUALCOMM Incorporated

Inventor： Jeffrey Junhao Xu ,  Mustafa Badaroglu ,  John Jianhong Zhu

IPC: H01L29/417 ,  H01L27/088 ,  H01L29/66 ,  H01L29/10 ,  H01L29/06 ,  H01L29/16 ,  H01L29/08 ,  H01L29/78

CPC classification number: H01L29/41791 ,  H01L27/0886 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/16 ,  H01L29/165 ,  H01L29/41766 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/785

Abstract: Semiconductor devices employing reduced area conformal contacts for reducing parasitic capacitance and improving performance, and related methods are disclosed. The area of the source/drain contacts for providing an electrical contract to a source/drain is reduced in size to reduce parasitic capacitance between a gate and the source/drain contacts for improved performance. To mitigate or avoid increase in contact resistance between the source/drain contacts and source/drain, a conformal contact layer of a desired thickness is disposed adjacent to the source/drain to reduce the source/drain contact resistance. Thus, the source/drain contacts may only have to extend down adjacent to an upper region of the source/drain to still achieve a desired, lower contact resistance with the source/drain contacts, which results in a reduced area source/drain contact for reducing parasitic capacitance.

公开(公告)号：US09985014B2

公开(公告)日：2018-05-29

申请号：US15266523

申请日：2016-09-15

Applicant: QUALCOMM Incorporated

Inventor： Jeffrey Junhao Xu ,  Mustafa Badaroglu ,  Da Yang

IPC: G06F17/50 ,  H01L27/00 ,  H01L27/02 ,  H01L29/423

CPC classification number: H01L27/0207 ,  G06F17/5068 ,  G06F17/5072 ,  G06F17/5077 ,  H01L27/11807 ,  H01L29/4232 ,  H01L2027/11811

Abstract: Minimum track standard cell circuits for reduced area are provided. In one aspect, a minimum track standard cell circuit employs a first high aspect ratio voltage rail disposed over a first one-half track and configured to provide a first voltage (e.g., VDD) to the minimum track standard cell circuit. A second high aspect ratio voltage rail is disposed over a second one-half track substantially parallel to the first high aspect ratio voltage rail. The second high aspect ratio voltage rail is configured to provide a second voltage less than the first voltage (e.g., VSS) to the minimum track standard cell circuit. The minimum track standard cell circuit employs multiple tracks disposed between the first and second one-half tracks. The number of tracks can be limited based on particular factors. Minimizing tracks reduces area compared to conventional standard cell circuits.

公开(公告)号：US20170110541A1

公开(公告)日：2017-04-20

申请号：US15198892

申请日：2016-06-30

Applicant: QUALCOMM Incorporated

Inventor： Jeffrey Junhao Xu ,  Stanley Seungchul Song ,  Da Yang ,  Vladimir Machkaoutsan ,  Mustafa Badaroglu ,  Choh Fei Yeap

IPC: H01L29/06 ,  H01L29/16 ,  H01L21/02 ,  H01L21/306 ,  H01L21/265 ,  H01L27/092 ,  H01L21/8238

CPC classification number: H01L29/0673 ,  H01L21/02603 ,  H01L21/26506 ,  H01L21/30604 ,  H01L21/823807 ,  H01L21/823821 ,  H01L27/0924 ,  H01L29/045 ,  H01L29/0649 ,  H01L29/125 ,  H01L29/16 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7853

Abstract: Aspects disclosed in the detailed description include nanowire channel structures of continuously stacked heterogeneous nanowires for complementary metal oxide semiconductor (CMOS) devices. Each of the nanowires has a top end portion and a bottom end portion that are narrower than a central portion. Furthermore, vertically adjacent nanowires are interconnected at the narrower top end portions and bottom end portions. This allows for connectivity between stacked nanowires and for having separation areas between vertically adjacent heterogeneous nanowires. Having the separation areas allows for gate material to be disposed over a large area of the heterogeneous nanowires and, therefore, provides strong gate control, a shorter nanowire channel structure, low parallel plate parasitic capacitance, and low parasitic channel capacitance. Having the nanowires be heterogeneous, i.e., fabricated using materials of different etching sensitivity, facilitates forming the particular cross section of the nanowires, thus eliminating the use of sacrificial masks/layers to form the heterogeneous nanowires.

公开(公告)号：US09502414B2

公开(公告)日：2016-11-22

申请号：US14633011

申请日：2015-02-26

Applicant: QUALCOMM Incorporated

Inventor： Vladimir Machkaoutsan ,  Mustafa Badaroglu ,  Jeffrey Junhao Xu ,  Stanley Seungchul Song ,  Choh Fei Yeap

IPC: H01L27/092 ,  H01L21/8238 ,  H01L29/423 ,  H01L29/06 ,  H01L21/3213 ,  H01L21/321

CPC classification number: H01L21/823828 ,  B82Y10/00 ,  H01L21/321 ,  H01L21/32133 ,  H01L21/823437 ,  H01L21/82345 ,  H01L21/823481 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823842 ,  H01L21/823878 ,  H01L27/0883 ,  H01L27/0886 ,  H01L27/092 ,  H01L27/0922 ,  H01L27/0924 ,  H01L29/0642 ,  H01L29/0669 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66803 ,  H01L29/775 ,  H01L29/785

Abstract: An integrated circuit (IC) device may include a first active transistor of a first-type in a first-type region. The first active transistor may have a first-type work function material and a low channel dopant concentration in an active portion of the first active transistor. The IC device may also include a first isolation transistor of the first-type in the first-type region. The second active transistor may have a second-type work function material and the low channel dopant concentration in an active portion of the first isolation transistor. The first isolation transistor may be arranged adjacent to the first active transistor.

Abstract translation: 集成电路（IC）装置可以包括在第一类型区域中的第一类型的第一有源晶体管。 第一有源晶体管可以在第一有源晶体管的有效部分中具有第一类型功函数材料和低通道掺杂剂浓度。 IC器件还可以包括在第一类型区域中的第一类型的第一隔离晶体管。 第二有源晶体管可以具有第二类型功函数材料，并且第一隔离晶体管的有源部分中的低通道掺杂剂浓度。 第一隔离晶体管可以布置成与第一有源晶体管相邻。

公开(公告)号：US20160225817A1

公开(公告)日：2016-08-04

申请号：US14609169

申请日：2015-01-29

Applicant: QUALCOMM Incorporated

Inventor： Vladimir Machkaoutsan ,  Matthias Georg Gottwald ,  Mustafa Badaroglu ,  Jimmy Kan ,  Kangho Lee ,  Yu Lu ,  Chando Park

IPC: H01L27/22 ,  H01L43/08 ,  H01L43/12 ,  H01L43/02

CPC classification number: H01L43/12 ,  H01L27/222 ,  H01L27/228 ,  H01L43/02 ,  H01L43/08

Abstract: A semiconductor device includes a first magnetic tunnel junction (MTJ) device, a second MTJ device, and a top electrode. The first MTJ device includes a barrier layer. The second MTJ device includes the barrier layer. The top electrode is coupled to the first MTJ device and the second MTJ device.

Abstract translation: 半导体器件包括第一磁性隧道结（MTJ）器件，第二MTJ器件和顶部电极。 第一MTJ装置包括阻挡层。 第二MTJ装置包括阻挡层。 顶部电极耦合到第一MTJ装置和第二MTJ装置。

公开(公告)号：US20150255571A1

公开(公告)日：2015-09-10

申请号：US14341568

申请日：2014-07-25

Applicant: QUALCOMM Incorporated

Inventor： Jeffrey Junhao Xu ,  Kern Rim ,  John Jianhong Zhu ,  Stanley Seungchul Song ,  Mustafa Badaroglu ,  Vladimir Machkaoutsan ,  Da Yang ,  Choh Fei Yeap

IPC: H01L29/66 ,  H01L29/78

CPC classification number: H01L29/6681 ,  H01L29/4991 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

Abstract: In a particular embodiment, a method includes forming a first spacer structure on a dummy gate of a semiconductor device and forming a sacrificial spacer on the first spacer structure. The method also includes etching a structure of the semiconductor device to create an opening, removing the sacrificial spacer via the opening, and depositing a material to close to define a gap.

Abstract translation: 在特定实施例中，一种方法包括在半导体器件的伪栅极上形成第一间隔结构，并在第一间隔物结构上形成牺牲隔离物。 该方法还包括蚀刻半导体器件的结构以形成开口，经由开口去除牺牲隔离物，以及沉积材料以限定间隙。

公开(公告)号：US20240282729A1

公开(公告)日：2024-08-22

申请号：US18171428

申请日：2023-02-20

Applicant: QUALCOMM Incorporated

Inventor： Mustafa Badaroglu ,  Zhongze Wang

IPC: H01L23/00 ,  H01L23/48 ,  H01L23/528 ,  H10B80/00

CPC classification number: H01L24/06 ,  H01L23/481 ,  H01L23/5286 ,  H01L24/02 ,  H01L24/05 ,  H10B80/00 ,  H01L24/16 ,  H01L24/17 ,  H01L2224/02372 ,  H01L2224/02381 ,  H01L2224/05548 ,  H01L2224/0557 ,  H01L2224/0603 ,  H01L2224/06182 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/1703 ,  H01L2224/17181 ,  H01L2924/1431 ,  H01L2924/1436 ,  H01L2924/1437

Abstract: A 3D IC package includes a first package die having a first side coupled to a package substrate and a second side coupled to a second package die. The first package die includes vertical interconnects to provide interconnections between the second package die and the package substrate. The vertical interconnects each extend vertically between a first die contact on the first side of the first package die and a second die contact on the second side of the first package die. The second package die couples to the second die contacts of the first package die to form power and/or signal interconnects between the package substrate and the second package die. Horizontal interconnects in a distribution layer on the first side of the first package die distribute power and signals horizontally between the first die contacts and the vertical interconnects.