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    Performing XNOR equivalent operations by adjusting column thresholds of a compute-in-memory array
    21.
    发明授权
    Performing XNOR equivalent operations by adjusting column thresholds of a compute-in-memory array 有权

    公开(公告)号：US11562212B2

    公开(公告)日：2023-01-24

    申请号：US16565308

    申请日：2019-09-09

    Applicant: QUALCOMM Incorporated

    Inventor： Zhongze Wang ,  Edward Teague ,  Max Welling

    IPC: G06N3/04 ,  G06N3/08

    Abstract: A method performs XNOR-equivalent operations by adjusting column thresholds of a compute-in-memory array of an artificial neural network. The method includes adjusting an activation threshold generated for each column of the compute-in-memory array based on a function of a weight value and an activation value. The method also includes calculating a conversion bias current reference based on an input value from an input vector to the compute-in-memory array, the compute-in-memory array being programmed with a set of weights. The adjusted activation threshold and the conversion bias current reference are used as a threshold for determining the output values of the compute-in-memory array.

    Fast digital multiply-accumulate (MAC) by fast digital multiplication circuit
    22.
    发明授权
    Fast digital multiply-accumulate (MAC) by fast digital multiplication circuit 有权

    公开(公告)号：US11474786B2

    公开(公告)日：2022-10-18

    申请号：US16778749

    申请日：2020-01-31

    Applicant: QUALCOMM Incorporated

    Inventor： Xia Li ,  Zhongze Wang ,  Periannan Chidambaram

    IPC: G06F7/533 ,  G06F7/53 ,  G06F7/523

    Abstract: Certain aspects provide methods and apparatus for multiplication of digital signals. In accordance with certain aspects, a multiplication circuit may be used to multiply a portion of a first digital input signal with a portion of a second digital input signal via a first multiplier circuit to generate a first multiplication signal, and multiply another portion of the first digital input signal with another portion of the second digital input signal via a second multiplier circuit to generate a second multiplication signal. A third multiplier circuit and multiple adder circuits may be used to generate an output of the multiplication circuit based on the first and second multiplication signals.

    Compute-in-memory (CIM) binary multiplier
    23.
    发明授权
    Compute-in-memory (CIM) binary multiplier 有权

    公开(公告)号：US11340867B2

    公开(公告)日：2022-05-24

    申请号：US16807562

    申请日：2020-03-03

    Applicant: QUALCOMM Incorporated

    Inventor： Xia Li ,  Zhongze Wang ,  Periannan Chidambaram

    IPC: G06F7/46

    Abstract: Certain aspects provide methods and apparatus for binary computation. An example circuit for such computation generally includes a memory cell having at least one of a bit-line or a complementary bit-line; a computation circuit coupled to a computation input node of the circuit and the bit-line or the complementary bit-line; and an adder coupled to the computation circuit, wherein the computation circuit comprises a first n-type metal-oxide-semiconductor (NMOS) transistor coupled to the memory cell, and a first p-type metal-oxide-semiconductor (PMOS) transistor coupled to the memory cell, drains of the first NMOS and PMOS transistors being coupled to the adder, wherein a source of the first PMOS transistor is coupled to a reference potential node, and wherein a source of the first NMOS transistor is coupled to the computation input node.

    MULTI-BIT COMPUTE-IN-MEMORY (CIM) ARRAYS EMPLOYING BIT CELL CIRCUITS OPTIMIZED FOR ACCURACY AND POWER EFFICIENCY
    24.
    发明申请
    MULTI-BIT COMPUTE-IN-MEMORY (CIM) ARRAYS EMPLOYING BIT CELL CIRCUITS OPTIMIZED FOR ACCURACY AND POWER EFFICIENCY 有权

    公开(公告)号：US20210349689A1

    公开(公告)日：2021-11-11

    申请号：US16868202

    申请日：2020-05-06

    Applicant: QUALCOMM Incorporated

    Inventor： Ye Lu ,  Zhongze Wang ,  Periannan Chidambaram

    IPC: G06F7/523 ,  G11C11/412 ,  G11C11/419

    Abstract: A bit cell circuit of a most-significant bit (MSB) of a multi-bit product generated in an array of bit cells in a compute-in-memory (CIM) array circuit is configured to receive a higher supply voltage than a supply voltage provided to a bit cell circuit of another bit cell corresponding to another bit of the multi-bit product. A bit cell circuit receiving a higher supply voltage increases a voltage difference between increments of an accumulated voltage, which can increase accuracy of an analog-to-digital converter determining a pop-count. A bit cell circuit of the MSB in the CIM array circuit receives the higher supply voltage to increase accuracy of the MSB which increases accuracy of the CIM array circuit output. A capacitance of a capacitor in the bit cell circuit of the MSB is smaller to avoid an increase in energy consumption due to the higher voltage.

    Integrated circuit device featuring an antifuse and method of making same
    28.
    发明授权
    Integrated circuit device featuring an antifuse and method of making same 有权
    具有反熔丝的集成电路器件及其制造方法

    公开(公告)号：US09502424B2

    公开(公告)日：2016-11-22

    申请号：US13684107

    申请日：2012-11-21

    Applicant: QUALCOMM Incorporated

    Inventor： Zhongze Wang ,  John Jianhong Zhu ,  Xia Li

    IPC: H01L27/112 ,  H01L21/8239 ,  G11C17/16 ,  H01L23/522 ,  H01L23/525 ,  H01L49/02 ,  H01L27/105

    CPC classification number: H01L27/11206 ,  G11C17/16 ,  G11C17/165 ,  H01L21/8239 ,  H01L23/5228 ,  H01L23/5252 ,  H01L27/1052 ,  H01L27/11286 ,  H01L28/24 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: One feature pertains to an integrated circuit, comprising an access transistor and an antifuse. The access transistor includes at least one source/drain region, and the antifuse has a conductor-insulator-conductor structure. The antifuse includes a first conductor that acts as a first electrode, and also includes an antifuse dielectric, and a second conductor. A first surface of the first electrode is coupled to a first surface of the antifuse dielectric, a second surface of the antifuse dielectric is coupled to a first surface of the second conductor. The second conductor is electrically coupled to the access transistor's source/drain region. The antifuse is adapted to transition from an open circuit state to a closed circuit state if a programming voltage Vpp greater than or equal to an antifuse dielectric breakdown voltage is applied between the first electrode and the second conductor.

    Abstract translation: 一个特征涉及一种集成电路，包括存取晶体管和反熔丝。 存取晶体管包括至少一个源极/漏极区域，反熔丝具有导体 - 绝缘体 - 导体结构。 反熔丝包括用作第一电极的第一导体，并且还包括反熔丝电介质和第二导体。 第一电极的第一表面耦合到反熔丝电介质的第一表面，反熔丝电介质的第二表面耦合到第二导体的第一表面。 第二导体电耦合到存取晶体管的源/漏区。 如果在第一电极和第二导体之间施加大于或等于抗熔丝电介质击穿电压的编程电压Vpp，则反熔丝适于从开路状态转换到闭合电路状态。

    Shared global read and write word lines
    29.
    发明授权
    Shared global read and write word lines 有权
    共享全局读写字线

    公开(公告)号：US09455026B2

    公开(公告)日：2016-09-27

    申请号：US14546980

    申请日：2014-11-18

    Applicant: QUALCOMM Incorporated

    Inventor： Niladri Narayan Mojumder ,  Stanley Seungchul Song ,  Zhongze Wang ,  Ping Liu ,  Kern Rim ,  Choh Fei Yeap

    IPC: G11C11/00 ,  G11C11/419 ,  G11C8/14 ,  H01L27/06 ,  G11C8/16

    CPC classification number: G11C11/419 ,  G11C8/14 ,  G11C8/16 ,  H01L27/0688 ,  H01L27/1104

    Abstract: An apparatus includes an array of bit cells that include a first row of bit cells and a second row of bit cells. The apparatus also includes a first global read word line configured to be selectively coupled to the first row of bit cells and to the second row of bit cells. The apparatus further includes a second global read word line configured to be selectively coupled to the first row of bit cells and to the second row of bit cells. The apparatus also includes a global write word line configured to be selectively coupled to the first row of bit cells and to the second row of bit cells. The first global read word line, the second global read word line, and the global write word line are located in a common metal layer.

    Abstract translation: 一种装置包括包括第一行位单元和第二行位单元的位单元阵列。 该装置还包括被配置为选择性地耦合到第一行位单元和第二行位单元的第一全局读取字线。 该装置还包括被配置为选择性地耦合到第一行位单元和第二行位单元的第二全局读取字线。 该装置还包括全局写入字线，其被配置为选择性地耦合到第一行位单元和第二行位单元。 第一个全局读取字线，第二个全局读取字线和全局写入字线位于公共金属层中。

    MEMORY DEVICE WITH ADAPTIVE VOLTAGE SCALING BASED ON ERROR INFORMATION
    30.
    发明申请
    MEMORY DEVICE WITH ADAPTIVE VOLTAGE SCALING BASED ON ERROR INFORMATION 有权
    基于错误信息的具有自适应电压调节的存储器件

    公开(公告)号：US20160225436A1

    公开(公告)日：2016-08-04

    申请号：US14611056

    申请日：2015-01-30

    Applicant: QUALCOMM Incorporated

    Inventor： Zhongze Wang ,  Niladri Narayan Mojumder ,  Jonathan Liu ,  Choh Fei Yeap

    IPC: G11C11/417 ,  G06F11/07

    CPC classification number: G11C11/417 ,  G06F11/073 ,  G06F11/076 ,  G06F11/0793 ,  G11C5/14 ,  G11C5/147 ,  G11C7/1045 ,  G11C7/22 ,  G11C29/021 ,  G11C29/028 ,  G11C2207/2254

    Abstract: A method of operation of a memory device includes, for each operating frequency of multiple operating frequencies, determining a target voltage level of a supply voltage. For example, a first target voltage level for a first operating frequency of the multiple operating frequencies is determined. The method includes accessing first data from the memory device while the memory device is operating at the first operating frequency and is powered by the supply voltage having a first voltage level. The method includes determining a first number of errors associated with the first data. The method further includes, in response to the first number of errors satisfying a threshold, adjusting the supply voltage to a second voltage level that is greater than the first voltage level.

    Abstract translation: 对于多个工作频率的每个工作频率，存储器件的操作方法包括确定电源电压的目标电压电平。 例如，确定用于多个工作频率的第一工作频率的第一目标电压电平。 该方法包括当存储器件在第一工作频率下操作并由具有第一电压电平的电源供电时从存储器件存取第一数据。 该方法包括确定与第一数据相关联的第一数量的错误。 该方法还包括响应于满足阈值的第一数量的误差，将电源电压调整到大于第一电压电平的第二电压电平。

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