公开(公告)号：US20130154006A1

公开(公告)日：2013-06-20

申请号：US13649284

申请日：2012-10-11

Applicant: International Business Machines Corporation

Inventor： Veeraraghavan S. Basker ,  Chung-Hsun Lin ,  Tenko Yamashita ,  Chun-Chen Yeh

IPC: H01L27/12 ,  H01L21/84

CPC classification number: H01L27/1211 ,  H01L29/0649 ,  H01L29/41791 ,  H01L29/45 ,  H01L29/66795 ,  H01L29/785 ,  H01L2029/7858

Abstract: FinFETS and methods for making FinFETs with a vertical silicide structure. A method includes providing a substrate with a plurality of fins, forming a gate stack above the substrate wherein the gate stack has at least one sidewall and forming an off-set spacer adjacent the gate stack sidewall. The method also includes growing an epitaxial film which merges the fins to form an epi-merge layer, forming a field oxide layer adjacent to at least a portion of the off-set spacer and removing a portion of the field oxide layer to expose a portion of the epi-merge-layer. The method further includes removing at least part of the exposed portion of the epi-merge-layer to form an epi-merge sidewall and an epi-merge spacer region and forming a silicide within the epi-merge sidewall to form a silicide layer and two silicide sidewalls.

Abstract translation: FinFET和用于制造具有垂直硅化物结构的FinFET的方法。 一种方法包括提供具有多个翅片的基板，在基板上形成栅极堆叠，其中栅极堆叠具有至少一个侧壁并形成邻近栅极堆叠侧壁的偏置间隔物。 该方法还包括生长外延膜，其将翅片合并以形成外延合并层，形成与偏置间隔物的至少一部分相邻的场氧化物层，并去除场氧化物层的一部分以暴露部分 的外延合并层。 该方法还包括去除外延合并层的暴露部分的至少一部分以形成外延合并侧壁和外延合并间隔区，并在外延合并侧壁内形成硅化物以形成硅化物层和二 硅化物侧壁

公开(公告)号：US10600680B2

公开(公告)日：2020-03-24

申请号：US16144433

申请日：2018-09-27

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Markus Brink ,  Michael A. Guillorn ,  Chung-Hsun Lin ,  HsinYu Tsai

IPC: H01L21/311 ,  H01L21/768 ,  H01L21/02 ,  H01L23/528 ,  H01L23/522 ,  H01L23/532 ,  G03F7/00

Abstract: A method of forming metal lines that are aligned to underlying metal features that includes forming a neutral layer atop a hardmask layer that is overlying a dielectric layer. The neutral layer is composed of a neutral charged di-block polymer. Patterning the neutral layer, the hardmask layer and the dielectric layer to provide openings that are filled with a metal material to provide metal features. A self-assembled di-block copolymer material is deposited on a patterned surface of the neutral layer and the metal features. The self-assembled di-block copolymer material includes a first block composition with a first affinity for alignment to the metal features. The first block composition of the self-assembled di-block copolymer is converted to a metal that is self-aligned to the metal features.

公开(公告)号：US09859122B2

公开(公告)日：2018-01-02

申请号：US15406096

申请日：2017-01-13

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Anthony I. Chou ,  Arvind Kumar ,  Chung-Hsun Lin ,  Shreesh Narasimha ,  Claude Ortolland ,  Jonathan T. Shaw

IPC: H01L21/28 ,  H01L29/51 ,  H01L29/40 ,  H01L29/66 ,  H01L21/02 ,  H01L29/423

CPC classification number: H01L21/28158 ,  H01L21/02181 ,  H01L21/0223 ,  H01L21/02247 ,  H01L21/02255 ,  H01L21/02323 ,  H01L21/02332 ,  H01L21/265 ,  H01L21/26586 ,  H01L21/28176 ,  H01L21/28185 ,  H01L21/283 ,  H01L21/3065 ,  H01L21/3085 ,  H01L21/31155 ,  H01L21/324 ,  H01L21/426 ,  H01L21/823462 ,  H01L21/845 ,  H01L29/401 ,  H01L29/41791 ,  H01L29/42356 ,  H01L29/42368 ,  H01L29/4238 ,  H01L29/511 ,  H01L29/512 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7856

Abstract: An asymmetric high-k dielectric for reduced gate induced drain leakage in high-k MOSFETs and methods of manufacture are disclosed. The method includes performing an implant process on a high-k dielectric sidewall of a gate structure. The method further includes performing an oxygen annealing process to grow an oxide region on a drain side of the gate structure, while inhibiting oxide growth on a source side of the gate structure adjacent to a source region.

公开(公告)号：US09768071B2

公开(公告)日：2017-09-19

申请号：US15159259

申请日：2016-05-19

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Anthony I. Chou ,  Arvind Kumar ,  Chung-Hsun Lin ,  Shreesh Narasimha ,  Claude Ortolland ,  Jonathan T. Shaw

IPC: H01L21/28 ,  H01L21/8234 ,  H01L21/3065 ,  H01L29/66 ,  H01L21/308 ,  H01L21/324 ,  H01L21/283 ,  H01L29/423 ,  H01L21/02

CPC classification number: H01L21/28158 ,  H01L21/02181 ,  H01L21/0223 ,  H01L21/02247 ,  H01L21/02255 ,  H01L21/02323 ,  H01L21/02332 ,  H01L21/265 ,  H01L21/26586 ,  H01L21/28176 ,  H01L21/28185 ,  H01L21/283 ,  H01L21/3065 ,  H01L21/3085 ,  H01L21/31155 ,  H01L21/324 ,  H01L21/426 ,  H01L21/823462 ,  H01L21/845 ,  H01L29/401 ,  H01L29/41791 ,  H01L29/42356 ,  H01L29/42368 ,  H01L29/4238 ,  H01L29/511 ,  H01L29/512 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7856

Abstract: An asymmetric high-k dielectric for reduced gate induced drain leakage in high-k MOSFETs and methods of manufacture are disclosed. The method includes performing an implant process on a high-k dielectric sidewall of a gate structure. The method further includes performing an oxygen annealing process to grow an oxide region on a drain side of the gate structure, while inhibiting oxide growth on a source side of the gate structure adjacent to a source region.

公开(公告)号：US09577061B2

公开(公告)日：2017-02-21

申请号：US15159269

申请日：2016-05-19

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Anthony I. Chou ,  Arvind Kumar ,  Chung-Hsun Lin ,  Shreesh Narasimha ,  Claude Ortolland ,  Jonathan T. Shaw

IPC: H01L29/423 ,  H01L29/51 ,  H01L29/78 ,  H01L29/417 ,  H01L21/28 ,  H01L21/02 ,  H01L21/8234

CPC classification number: H01L21/28158 ,  H01L21/02181 ,  H01L21/0223 ,  H01L21/02247 ,  H01L21/02255 ,  H01L21/02323 ,  H01L21/02332 ,  H01L21/265 ,  H01L21/26586 ,  H01L21/28176 ,  H01L21/28185 ,  H01L21/283 ,  H01L21/3065 ,  H01L21/3085 ,  H01L21/31155 ,  H01L21/324 ,  H01L21/426 ,  H01L21/823462 ,  H01L21/845 ,  H01L29/401 ,  H01L29/41791 ,  H01L29/42356 ,  H01L29/42368 ,  H01L29/4238 ,  H01L29/511 ,  H01L29/512 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7856

Abstract: An asymmetric high-k dielectric for reduced gate induced drain leakage in high-k MOSFETs and methods of manufacture are disclosed. The method includes performing an implant process on a high-k dielectric sidewall of a gate structure. The method further includes performing an oxygen annealing process to grow an oxide region on a drain side of the gate structure, while inhibiting oxide growth on a source side of the gate structure adjacent to a source region.

Abstract translation: 公开了一种用于在高k MOSFET中减小栅极感应漏极泄漏的非对称高k电介质和制造方法。 该方法包括在栅极结构的高k电介质侧壁上执行注入工艺。 该方法还包括进行氧退火处理，以在栅极结构的漏极侧生长氧化物区域，同时抑制邻近源极区域的栅极结构的源极上的氧化物生长。

公开(公告)号：US20160365280A1

公开(公告)日：2016-12-15

申请号：US14738284

申请日：2015-06-12

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Markus Brink ,  Michael A. Guillorn ,  Chung-Hsun Lin ,  HsinYu Tsai

IPC: H01L21/768 ,  H01L23/532 ,  H01L23/528 ,  H01L23/522 ,  H01L21/02 ,  H01L21/311

CPC classification number: H01L21/76807 ,  G03F7/0002 ,  H01L21/02118 ,  H01L21/31133 ,  H01L21/31144 ,  H01L21/76802 ,  H01L21/76816 ,  H01L21/76823 ,  H01L21/76838 ,  H01L21/76849 ,  H01L21/76877 ,  H01L21/76879 ,  H01L21/76897 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/5329

Abstract: A method of forming metal lines that are aligned to underlying metal features that includes forming a neutral layer atop a hardmask layer that is overlying a dielectric layer. The neutral layer is composed of a neutral charged di-block polymer. Patterning the neutral layer, the hardmask layer and the dielectric layer to provide openings that are filled with a metal material to provide metal features. A self-assembled di-block copolymer material is deposited on a patterned surface of the neutral layer and the metal features. The self-assembled di-block copolymer material includes a first block composition with a first affinity for alignment to the metal features. The first block composition of the self-assembled di-block copolymer is converted to a metal that is self-aligned to the metal features.

Abstract translation: 形成与下面的金属特征对准的金属线的方法，其包括在覆盖介电层的硬掩模层的顶部形成中性层。 中性层由中性带电的二嵌段聚合物组成。 对中性层，硬掩模层和电介质层进行图案化以提供填充有金属材料以提供金属特征的开口。 自组装的二嵌段共聚物材料沉积在中性层的图案化表面和金属特征上。 自组装二嵌段共聚物材料包括具有与金属特征对准的第一亲和性的第一嵌段组合物。 自组装二嵌段共聚物的第一嵌段组合物转化成与金属特征自对准的金属。

公开(公告)号：US09324801B2

公开(公告)日：2016-04-26

申请号：US14511837

申请日：2014-10-10

Applicant: International Business Machines Corporation

Inventor： Isaac Lauer ,  Chung-Hsun Lin ,  Jeffrey W. Sleight

IPC: H01L29/10 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/1054 ,  H01L29/06 ,  H01L29/0669 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66795 ,  H01L29/7842 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/78696

Abstract: Fin stacks including a silicon germanium alloy portion and a silicon portion are formed on a surface of a substrate. Sacrificial gate structures are then formed straddling each fin stack. Silicon germanium alloy portions that are exposed are oxidized, while silicon germanium alloy portions that are covered by the sacrificial gate structures are not oxidized. A dielectric material having a topmost surface that is coplanar with a topmost surface of each sacrificial gate structure is formed, and thereafter each sacrificial gate structure is removed. Non-oxidized silicon germanium alloy portions are removed suspending silicon portions that were present on each non-oxidized silicon germanium alloy portion. A functional gate structure is then formed around each suspended silicon portion. The oxidized silicon germanium alloy portions remain and provide stress to a channel portion of the suspended silicon portions.

Abstract translation: 在基板的表面上形成包括硅锗合金部和硅部的散热片。 牺牲栅结构然后形成跨越每个鳍堆叠。 暴露的硅锗合金部分被氧化，而被牺牲栅极结构覆盖的硅锗合金部分不被氧化。 形成具有与每个牺牲栅极结构的最顶表面共面的最顶表面的电介质材料，然后除去每个牺牲栅极结构。 去除非氧化硅锗合金部分，悬浮在每个未氧化的硅锗合金部分上存在的硅部分。 然后在每个悬置的硅部分周围形成功能门结构。 氧化硅锗合金部分保留并向悬浮硅部分的通道部分提供应力。

公开(公告)号：US20150325470A1

公开(公告)日：2015-11-12

申请号：US14272691

申请日：2014-05-08

Applicant: International Business Machines Corporation

Inventor： Josephine B. Chang ,  Michael A. Guillorn ,  Chung-Hsun Lin ,  HsinYu Tsai

IPC: H01L21/768 ,  H01L23/528 ,  H01L21/311

CPC classification number: H01L21/76816 ,  H01L21/02118 ,  H01L21/0337 ,  H01L21/31144 ,  H01L21/76828 ,  H01L21/76831 ,  H01L21/76877 ,  H01L21/76895 ,  H01L22/34 ,  H01L23/528 ,  H01L2924/0002 ,  H01L2924/00

Abstract: In one aspect, a DSA-based method for forming a Kelvin-testable structure includes the following steps. A guide pattern is formed on a substrate which defines i) multiple pad regions of the Kelvin-testable structure and ii) a region interconnecting two of the pad regions on the substrate. A self-assembly material is deposited onto the substrate and is annealed at a temperature/duration sufficient to cause it to undergo self-assembly to form a self-assembled pattern on the substrate, wherein the self-assembly is directed by the guide pattern such that the self-assembled material in the region interconnecting the two pad regions forms multiple straight lines. A pattern of the self-assembled material is transferred to the substrate forming multiple lines in the substrate, wherein the pattern of the self-assembled material is configured such that only a given one of the lines is a continuous line between the two pad regions on the substrate.

公开(公告)号：US09177923B2

公开(公告)日：2015-11-03

申请号：US14519731

申请日：2014-10-21

Applicant: International Business Machines Corporation

Inventor： Daeik Kim ,  Chandrasekharan Kothandaraman ,  Chung-Hsun Lin ,  John M. Safran

IPC: H01L21/44 ,  H01L23/04 ,  H01L23/58 ,  H01L21/768 ,  H01L23/48 ,  H01L23/498 ,  H01L23/00

CPC classification number: H01L23/58 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/585 ,  H01L24/05 ,  H01L24/06 ,  H01L2224/0557 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/05684 ,  H01L2224/06181 ,  H01L2924/00014 ,  H01L2924/10253 ,  H01L2924/1306 ,  H01L2924/3025 ,  H01L2924/3512 ,  H01L2224/05552

Abstract: A semiconductor apparatus includes a substrate structure including a silicon substrate layer, a conductive through-substrate via extending through the silicon substrate layer. The apparatus further includes a semiconductor device located in the substrate structure and a conductive wall located between the through-substrate via and the semiconductor device. The conductive wall is in electrical contact with the silicon substrate layer.

Abstract translation: 半导体装置包括：衬底结构，其包括硅衬底层，通过硅衬底层延伸的导电贯通衬底。 该设备还包括位于衬底结构中的半导体器件和位于贯穿衬底通孔和半导体器件之间的导电壁。 导电壁与硅衬底层电接触。

公开(公告)号：US09087909B2

公开(公告)日：2015-07-21

申请号：US13961003

申请日：2013-08-07

Applicant: International Business Machines Corporation

Inventor： Chung-Hsun Lin ,  Yu-Shiang Lin ,  Shih-Hsien Lo ,  Joel A. Silberman

IPC: H01L27/12 ,  H01L29/786 ,  H01L29/66 ,  H01L29/06 ,  H01L23/48

CPC classification number: H01L29/78696 ,  H01L21/3065 ,  H01L21/76898 ,  H01L21/84 ,  H01L23/481 ,  H01L27/1203 ,  H01L27/1211 ,  H01L29/0665 ,  H01L29/0673 ,  H01L29/66742 ,  H01L29/66772 ,  H01L29/78651 ,  H01L2924/0002 ,  H01L2924/00

Abstract: In one aspect, a method for forming an electronic device includes the following steps. An ETSOI layer of an ETSOI wafer is patterned into one or more ETSOI segments each of the ETSOI segments having a width of from about 3 nm to about 20 nm. A gate electrode is formed over a portion of the one or more ETSOI segments which serves as a channel region of a transistor, wherein portions of the one or more ETSOI segments extending out from under the gate electrode serve as source and drain regions of the transistor. At least one TSV is formed in the ETSOI wafer adjacent to the transistor. An electronic device is also provided.

Abstract translation: 一方面，一种形成电子装置的方法包括以下步骤。 ETSOI晶片的ETSOI层被图案化成一个或多个ETSOI区段，每个ETSOI区段具有约3nm至约20nm的宽度。 在用作晶体管的沟道区的一个或多个ETSOI段的一部分上形成栅电极，其中从栅极下方延伸的一个或多个ETSOI区的部分用作晶体管的源极和漏极区 。 在与晶体管相邻的ETSOI晶片中形成至少一个TSV。 还提供电子设备。