公开(公告)号：US20240339424A1

公开(公告)日：2024-10-10

申请号：US18230793

申请日：2023-08-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei-Yu Chen ,  Chao-Wei Chiu ,  Hsin Liang Chen ,  Hao-Jan Pei ,  Hsiu-Jen Lin ,  Ching-Hua Hsieh

IPC: H01L23/00

CPC classification number: H01L24/13 ,  H01L24/11 ,  H01L2224/0401 ,  H01L2924/01322

Abstract: Embodiments provide a device structure and method of forming a device structure including an infill structure to capture solder materials within confines of openings of the infill structure. Metal pillars of one device can penetrate through a non-conductive film and contact solder regions of another device. A separate underfill is not needed.

公开(公告)号：US20240339420A1

公开(公告)日：2024-10-10

申请号：US18537960

申请日：2023-12-13

Applicant: SAMSUNG ELECTRONICS CO, LTD.

Inventor： JU BIN SEO ,  Seok Ho KIM ,  Kwang Jin MOON

IPC: H01L23/00 ,  H01L21/66

CPC classification number: H01L24/06 ,  H01L22/32 ,  H01L24/03 ,  H01L24/05 ,  H01L24/08 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L24/80 ,  H01L25/0657 ,  H01L25/18 ,  H01L2224/0345 ,  H01L2224/0346 ,  H01L2224/03845 ,  H01L2224/0392 ,  H01L2224/05022 ,  H01L2224/05084 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05181 ,  H01L2224/05184 ,  H01L2224/0557 ,  H01L2224/05573 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/05684 ,  H01L2224/0603 ,  H01L2224/06181 ,  H01L2224/06515 ,  H01L2224/13111 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/80357 ,  H01L2224/80379 ,  H01L2224/80896 ,  H01L2924/05042 ,  H01L2924/0544 ,  H01L2924/059 ,  H01L2924/1431 ,  H01L2924/1432 ,  H01L2924/1433 ,  H01L2924/1436 ,  H01L2924/1437 ,  H01L2924/1438 ,  H01L2924/1441 ,  H01L2924/1443 ,  H10B80/00

Abstract: A semiconductor package includes a substrate, a semiconductor layer on the substrate, a wiring structure on the semiconductor layer, a connection pad on and connected to the wiring structure, a test pad on and connected to the wiring structure, the test and connection pads being horizontally spaced from each other, a first liner film on the wiring structure and having a first bonding pad trench, a second liner film on the first liner film and having a second bonding pad trench, a first bonding pad including a barrier layer in contact with the first liner film and a metal layer on the barrier layer, and a second bonding pad filling an inner portion of the second bonding pad trench and in contact with the second liner film, wherein the second liner film integrally covers upper surfaces of the barrier layer and metal layer.

公开(公告)号：US20240332272A1

公开(公告)日：2024-10-03

申请号：US18190885

申请日：2023-03-27

Applicant: AMKOR TECHNOLOGY SINGAPORE HOLDING PTE. LTD.

Inventor： Sang Yun MA ,  Dong Hee KANG

IPC: H01L25/16 ,  H01L23/13 ,  H01L23/367 ,  H01L23/552

CPC classification number: H01L25/165 ,  H01L23/13 ,  H01L23/3675 ,  H01L23/552 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/33 ,  H01L24/73 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/13166 ,  H01L2224/13184 ,  H01L2224/16227 ,  H01L2224/2919 ,  H01L2224/29191 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/33181 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2924/0132 ,  H01L2924/0665 ,  H01L2924/069 ,  H01L2924/0695 ,  H01L2924/07025 ,  H01L2924/0715

Abstract: In one example, an electronic device includes a substrate with a substrate first side; a substrate second side opposite to the substrate first side, a substrate lateral side connecting the substrate first side to the substrate second side, a dielectric structure, and a conductive structure. A substrate dock includes a substrate dock base at the substrate first side and a first substrate dock sidewall extending upward from the substrate dock base. The substrate dock base and the first substrate dock sidewall define a substrate dock cavity. A cover structure includes a cover sidewall with a cover sidewall lower side. An interface material couples the cover sidewall to the substrate dock. An electronic component is coupled to the conductive structure. Other examples and related methods are also disclosed herein.

公开(公告)号：US20240332208A1

公开(公告)日：2024-10-03

申请号：US18226994

申请日：2023-07-27

Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.

Inventor： Chi Hyeon JEONG ,  Hyun Sang KWAK ,  Seong Hwan LEE

IPC: H01L23/552 ,  H01L23/13 ,  H01L23/498 ,  H01L23/538

CPC classification number: H01L23/552 ,  H01L23/13 ,  H01L23/49822 ,  H01L23/5385 ,  H01L24/13 ,  H01L24/16 ,  H01L25/0655 ,  H01L2224/13111 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/16227 ,  H01L2924/014

Abstract: A printed circuit board includes a substrate portion including a first insulating layer, a first wiring layer disposed on or within the first insulating layer, and a cavity penetrating through at least a portion of the first insulating layer; a connection structure disposed within the cavity of the substrate portion, and including a second insulating layer, a second wiring layer disposed on or within the second insulating layer, and a metal layer disposed on a lower surface and a side surface of the second insulating layer, wherein the metal layer is disposed on an outermost side of the connection structure.

公开(公告)号：US20240332202A1

公开(公告)日：2024-10-03

申请号：US18735194

申请日：2024-06-06

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Yu-Hung Lin ,  Chih-Wei Wu ,  Chia-Nan Yuan ,  Ying-Ching Shih ,  An-Jhih Su ,  Szu-Wei Lu ,  Ming-Shih Yeh ,  Der-Chyang Yeh

IPC: H01L23/538 ,  H01L21/56 ,  H01L21/768 ,  H01L23/00 ,  H01L23/29 ,  H01L23/31 ,  H01L23/48

CPC classification number: H01L23/5389 ,  H01L21/56 ,  H01L21/76898 ,  H01L23/295 ,  H01L23/3135 ,  H01L23/481 ,  H01L23/5381 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/24 ,  H01L24/25 ,  H01L24/82 ,  H01L2224/11462 ,  H01L2224/13025 ,  H01L2224/14181 ,  H01L2224/16145 ,  H01L2224/24105 ,  H01L2224/24146 ,  H01L2224/25171 ,  H01L2224/25174 ,  H01L2224/2518 ,  H01L2224/82101

Abstract: A package structure and method of forming the same are provided. The package structure includes a first die and a second die disposed side by side, a first encapsulant laterally encapsulating the first and second dies, a bridge die disposed over and connected to the first and second dies, and a second encapsulant. The bridge die includes a semiconductor substrate, a conductive via and an encapsulant layer. The semiconductor substrate has a through substrate via embedded therein. The conductive via is disposed over a back side of the semiconductor substrate and electrically connected to the through substrate via. The encapsulant layer is disposed over the back side of the semiconductor substrate and laterally encapsulates the conductive via. The second encapsulant is disposed over the first encapsulant and laterally encapsulates the bridge die.

公开(公告)号：US12107062B2

公开(公告)日：2024-10-01

申请号：US17694995

申请日：2022-03-15

Applicant: Texas Instruments Incorporated

Inventor： Rafael Jose Guevara

IPC: H01L23/00 ,  H01L23/498

CPC classification number: H01L24/13 ,  H01L24/05 ,  H01L24/11 ,  H01L24/16 ,  H01L23/49822 ,  H01L2224/02381 ,  H01L2224/0239 ,  H01L2224/05691 ,  H01L2224/11005 ,  H01L2224/11009 ,  H01L2224/11849 ,  H01L2224/13019 ,  H01L2224/13024 ,  H01L2224/13553 ,  H01L2224/13575 ,  H01L2224/16227 ,  H01L2224/16245 ,  H01L2924/381 ,  H01L2924/3841

Abstract: A semiconductor die includes a substrate including a semiconductor surface including circuitry electrically connected to die bond pads that include a first die bond pad exposed by a passivation layer, a top dielectric layer over the passivation layer, and a metal layer electrically connected to the first die bond pad. A pillar is on the metal layer over the first die bond pad, and a solder cap is on a top side of the pillar. The solder cap includes an essentially vertical sidewall portion generally beginning at a top corner edge of the pillar.

公开(公告)号：US20240321857A1

公开(公告)日：2024-09-26

申请号：US18736766

申请日：2024-06-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Juhyeon Kim ,  Hyoeun Kim ,  Sunkyoung Seo

IPC: H01L25/00 ,  H01L21/768 ,  H01L21/78 ,  H01L23/00 ,  H01L25/065

CPC classification number: H01L25/50 ,  H01L21/76898 ,  H01L21/78 ,  H01L24/03 ,  H01L24/80 ,  H01L24/94 ,  H01L24/97 ,  H01L24/08 ,  H01L24/13 ,  H01L25/0657 ,  H01L2224/0401 ,  H01L2224/08146 ,  H01L2224/80001 ,  H01L2225/06541

Abstract: A method of manufacturing a semiconductor package includes preparing a wafer structure having a first semiconductor substrate and a plurality of first front surface connection pads. A lower semiconductor chip having a preliminary semiconductor substrate and a plurality of second front surface connection pads are attached to the wafer structure such that the plurality of first front surface connection pads and the plurality of second front surface connection pads correspond to each other. A plurality of bonding pads is formed by bonding together the plurality of first front surface connection pads and the plurality of second front surface connection pads corresponding to each other. A second semiconductor substrate having a horizontal width that is less than that of the second wiring structure is formed by removing a portion of the preliminary semiconductor substrate.

公开(公告)号：US20240321851A1

公开(公告)日：2024-09-26

申请号：US18506346

申请日：2023-11-10

Applicant: SAMSUNG ELECTERONICS CO., LTD.

Inventor： CHOONGBIN YIM ,  Jongkook Kim ,  Chengtar Wu

IPC: H01L25/18 ,  H01L21/56 ,  H01L23/00 ,  H01L25/00 ,  H10B80/00

CPC classification number: H01L25/18 ,  H01L21/568 ,  H01L24/05 ,  H01L24/08 ,  H01L24/13 ,  H01L24/16 ,  H01L24/19 ,  H01L24/20 ,  H01L24/32 ,  H01L24/73 ,  H01L24/80 ,  H01L24/83 ,  H01L24/92 ,  H01L24/95 ,  H01L25/50 ,  H10B80/00 ,  H01L2224/0557 ,  H01L2224/05611 ,  H01L2224/05616 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/08145 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16145 ,  H01L2224/19 ,  H01L2224/214 ,  H01L2224/215 ,  H01L2224/32145 ,  H01L2224/73204 ,  H01L2224/80006 ,  H01L2224/80357 ,  H01L2224/80379 ,  H01L2224/80896 ,  H01L2224/83005 ,  H01L2224/83862 ,  H01L2224/92125 ,  H01L2224/95001 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/0504 ,  H01L2924/05442 ,  H01L2924/059

Abstract: A semiconductor package includes: a redistribution layer structure; a first semiconductor die and a second semiconductor die disposed on the redistribution layer structure; a bridge die disposed on the first semiconductor die and the second semiconductor die and that electrically connects the first semiconductor die and the second semiconductor die to each other; and a molding material disposed on the redistribution layer structure and that molds of the first semiconductor die, the second semiconductor die, and the bridge die. A bottom surface of the first semiconductor die and a bottom surface of the second semiconductor die are coplanar with an upper surface of the redistribution layer structure.

公开(公告)号：US20240321800A1

公开(公告)日：2024-09-26

申请号：US18444786

申请日：2024-02-19

Applicant: E Ink Holdings Inc.

Inventor： Wenchuan Wang ,  Kuang-Heng Liang ,  Wen-Yu Kuo ,  Yen-Ze Huang ,  Jen-Shiun Huang

IPC: H01L23/00 ,  G02B26/00 ,  G02F1/167 ,  G02F1/1676 ,  G02F1/1677

CPC classification number: H01L24/16 ,  G02B26/005 ,  G02F1/1676 ,  G02F1/1677 ,  H01L24/05 ,  H01L24/13 ,  G02F1/167 ,  H01L24/14 ,  H01L2224/05541 ,  H01L2224/05555 ,  H01L2224/13007 ,  H01L2224/13013 ,  H01L2224/13014 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/14051 ,  H01L2224/14155 ,  H01L2224/16237 ,  H01L2924/1426

Abstract: A display device includes a driving circuit substrate, a display layer, an opposite substrate, and a conducting structure. The driving circuit substrate includes a first substrate and a driving circuit layer disposed on the first substrate. The driving circuit layer includes a display region, a peripheral region at the periphery of the display region, and a conducting pad located between the peripheral region and an edge of the first substrate. The opposite substrate includes a second substrate and an opposite electrode layer disposed on the second substrate. The display layer is located between the opposite electrode layer and the driving circuit layer. A conductive member of the conducting structure is connected between the conducting pad and the opposite electrode layer. The conducting structure has a first width. The peripheral region has a second width. The first width is less than or equal to 2.5 times the second width.

公开(公告)号：US20240321730A1

公开(公告)日：2024-09-26

申请号：US18189673

申请日：2023-03-24

Applicant: QUALCOMM Incorporated

Inventor： Hsiao-Tsung YEN ,  Xingyi HUA ,  Jeongil Jay KIM

IPC: H01L23/522

CPC classification number: H01L23/5227 ,  H01L28/10 ,  H01L24/02 ,  H01L24/03 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/19 ,  H01L24/20 ,  H01L2224/0231 ,  H01L2224/02381 ,  H01L2224/0346 ,  H01L2224/0401 ,  H01L2224/05572 ,  H01L2224/11849 ,  H01L2224/13021 ,  H01L2224/16227 ,  H01L2224/19 ,  H01L2224/2105

Abstract: An integrated device comprising a die substrate, a die interconnection portion coupled to the die substrate, and a stacked inductor that includes a first figure 8-shaped inductor and a second figure 8-shaped inductor. The stacked inductor may include a first spiral comprising a first origin and a first tail, a second spiral comprising a second origin and a second tail, a third spiral comprising a third origin and a third tail and a fourth spiral comprising a fourth origin and a fourth tail. The first spiral, the second spiral, the third spiral and the fourth spiral may form the first figure 8-shaped inductor and the second figure 8-shaped inductor. The stacked inductor may be located in the die interconnection.