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公开(公告)号：US12087696B2
公开(公告)日：2024-09-10
申请号：US18095900
申请日：2023-01-11
发明人： Sunkyoung Seo , Taehwan Kim , Hyunjung Song , Hyoeun Kim , Wonil Lee , Sanguk Han
IPC分类号： H01L23/48 , H01L23/00 , H01L23/367 , H01L23/538
CPC分类号： H01L23/5384 , H01L23/367 , H01L23/5385 , H01L23/5386 , H01L24/14
摘要： A semiconductor package includes a package substrate, a lower semiconductor device arranged on the package substrate and including first through electrodes, first lower connection bumps arranged between the package substrate and the lower semiconductor device and electrically connecting the package substrate to the first through electrodes, a connecting substrate arranged on the package substrate and including second through electrodes, second lower connection bumps arranged between the package substrate and the connecting substrate and electrically connecting the package substrate to the second through electrodes, and an upper semiconductor device arranged on the lower semiconductor device and electrically connected to the first through electrodes and the second through electrodes.
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公开(公告)号：US11923342B2
公开(公告)日：2024-03-05
申请号：US17705872
申请日：2022-03-28
发明人： Sanguk Han , Chajea Jo , Hyoeun Kim , Sunkyoung Seo
IPC分类号： H01L25/065 , H01L23/00 , H01L23/31
CPC分类号： H01L25/0657 , H01L23/3121 , H01L23/3135 , H01L24/13
摘要： A package-on-package type package includes a lower semiconductor package and an upper semiconductor package. The lower semiconductor package includes a first semiconductor device including a through electrode, a second semiconductor device disposed on the first semiconductor device and including a second through electrode electrically connected to the first through electrode, a first molding member covering a sidewall of at least one of the first semiconductor device and the second semiconductor device, a second molding member covering a sidewall of the first molding member, and an upper redistribution layer disposed on the second semiconductor device and electrically connected to the second through electrode.
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公开(公告)号：US11574873B2
公开(公告)日：2023-02-07
申请号：US17003639
申请日：2020-08-26
发明人： Sunkyoung Seo , Taehwan Kim , Hyunjung Song , Hyoeun Kim , Wonil Lee , Sanguk Han
IPC分类号： H01L23/367 , H01L23/538 , H01L23/00
摘要： A semiconductor package includes a package substrate, a lower semiconductor device arranged on the package substrate and including first through electrodes, first lower connection bumps arranged between the package substrate and the lower semiconductor device and electrically connecting the package substrate to the first through electrodes, a connecting substrate arranged on the package substrate and including second through electrodes, second lower connection bumps arranged between the package substrate and the connecting substrate and electrically connecting the package substrate to the second through electrodes, and an upper semiconductor device arranged on the lower semiconductor device and electrically connected to the first through electrodes and the second through electrodes.
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公开(公告)号：US11545512B2
公开(公告)日：2023-01-03
申请号：US17154890
申请日：2021-01-21
发明人： Chajea Jo , Ohguk Kwon , Hyoeun Kim , Seunghoon Yeon
IPC分类号： H01L27/146 , H04N5/225
摘要： An image sensor package comprises: an image sensor chip configured to convert light collected from an outside thereof into an electrical signal; a package substrate disposed under the image sensor chip the package substrate configured to process the electrical signal converted from the image sensor chip; a glass substrate disposed over the image sensor chip while being spaced apart from the image sensor chip; a seal pattern disposed between an upper surface of the package substrate and a lower surface of the glass substrate while surrounding the image sensor chip; and a protection pattern disposed on the package substrate outside the seal pattern, the protection pattern comprising a single-component material, wherein the seal pattern comprises a material different from the material of the protection pattern.
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公开(公告)号：US10651224B2
公开(公告)日：2020-05-12
申请号：US16058451
申请日：2018-08-08
发明人： Ji Hwang Kim , Chajea Jo , Hyoeun Kim , Jongbo Shim , Sang-uk Han
IPC分类号： H01L31/00 , H01L27/146 , H01L23/00
摘要： A semiconductor package includes a first semiconductor chip. A second semiconductor chip is below the first semiconductor chip. A third semiconductor chip is below the second semiconductor chip. The second semiconductor chip includes a first surface in direct contact with the first semiconductor chip, and a second surface facing the third semiconductor chip. A first redistribution pattern is on the second surface of the second semiconductor chip and is electrically connected to the third semiconductor chip. The third semiconductor chip includes a third surface facing the second semiconductor chip. A conductive pad is on the third surface.
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公开(公告)号：US11626385B2
公开(公告)日：2023-04-11
申请号：US17178327
申请日：2021-02-18
发明人： Namhoon Kim , Chajea Jo , Ohguk Kwon , Hyoeun Kim , Seunghoon Yeon
IPC分类号： H01L25/065 , H01L23/00
摘要： A semiconductor package includes a first semiconductor chip comprising a semiconductor substrate and a redistribution pattern on a top surface of the semiconductor substrate, the redistribution pattern having a hole exposing an inner sidewall of the redistribution pattern, a second semiconductor chip on a top surface of the first semiconductor chip, and a bump structure disposed between the first semiconductor chip and the second semiconductor chip. The bump structure is disposed in the hole and is in contact with the inner sidewall of the redistribution pattern.
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公开(公告)号：US11444060B2
公开(公告)日：2022-09-13
申请号：US16742341
申请日：2020-01-14
发明人： Sanguk Han , Chajea Jo , Hyoeun Kim , Sunkyoung Seo
IPC分类号： H01L25/065 , H01L23/00 , H01L23/31
摘要： A package-on-package type package includes a lower semiconductor package and an upper semiconductor package. The lower semiconductor package includes a first semiconductor device including a through electrode, a second semiconductor device disposed on the first semiconductor device and including a second through electrode electrically connected to the first through electrode, a first molding member covering a sidewall of at least one of the first semiconductor device and the second semiconductor device, a second molding member covering a sidewall of the first molding member, and an upper redistribution layer disposed on the second semiconductor device and electrically connected to the second through electrode.
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公开(公告)号：US11328966B2
公开(公告)日：2022-05-10
申请号：US16749620
申请日：2020-01-22
发明人： Hyoeun Kim , Yonghoe Cho , Sunkyoung Seo , Seunghoon Yeon , Sanguk Han
摘要： A chip-stacked semiconductor package includes a first chip including a first detection pad and a second detection pad; a second chip provided on the first chip, the second chip including a third detection pad facing the first detection pad and a fourth detection pad facing the second detection pad; and a first medium provided between the first detection pad and the third detection pad to connect the first detection pad to the third detection pad through the first medium, and a second medium, different from the first medium, provided between the second detection pad and the fourth detection pad to connect the second detection pad to the fourth detection pad through the second medium.
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公开(公告)号：US20190214423A1
公开(公告)日：2019-07-11
申请号：US16058451
申请日：2018-08-08
发明人： Ji Hwang Kim , Chajea Jo , Hyoeun Kim , Jongbo Shim , Sang-uk Han
IPC分类号： H01L27/146 , H01L23/00
CPC分类号： H01L27/14634 , H01L24/05 , H01L24/08 , H01L24/09 , H01L24/16 , H01L27/14618 , H01L27/14632 , H01L27/14636 , H01L27/14687 , H01L2224/02372 , H01L2224/02377 , H01L2224/02381 , H01L2224/0557 , H01L2224/08145 , H01L2224/09181 , H01L2224/16104 , H01L2224/16145
摘要： A semiconductor package includes a first semiconductor chip. A second semiconductor chip is below the first semiconductor chip. A third semiconductor chip is below the second semiconductor chip. The second semiconductor chip includes a first surface in direct contact with the first semiconductor chip, and a second surface facing the third semiconductor chip. A first redistribution pattern is on the second surface of the second semiconductor chip and is electrically connected to the third semiconductor chip. The third semiconductor chip includes a third surface facing the second semiconductor chip. A conductive pad is on the third surface.
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公开(公告)号：US20240321857A1
公开(公告)日：2024-09-26
申请号：US18736766
申请日：2024-06-07
发明人： Juhyeon Kim , Hyoeun Kim , Sunkyoung Seo
IPC分类号： H01L25/00 , H01L21/768 , H01L21/78 , H01L23/00 , H01L25/065
CPC分类号： H01L25/50 , H01L21/76898 , H01L21/78 , H01L24/03 , H01L24/80 , H01L24/94 , H01L24/97 , H01L24/08 , H01L24/13 , H01L25/0657 , H01L2224/0401 , H01L2224/08146 , H01L2224/80001 , H01L2225/06541
摘要： A method of manufacturing a semiconductor package includes preparing a wafer structure having a first semiconductor substrate and a plurality of first front surface connection pads. A lower semiconductor chip having a preliminary semiconductor substrate and a plurality of second front surface connection pads are attached to the wafer structure such that the plurality of first front surface connection pads and the plurality of second front surface connection pads correspond to each other. A plurality of bonding pads is formed by bonding together the plurality of first front surface connection pads and the plurality of second front surface connection pads corresponding to each other. A second semiconductor substrate having a horizontal width that is less than that of the second wiring structure is formed by removing a portion of the preliminary semiconductor substrate.
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