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公开(公告)号：US11158603B2
公开(公告)日：2021-10-26
申请号：US16298476
申请日：2019-03-11
发明人： Hyoeun Kim , Ji Hwang Kim , Jisun Yang , Seunghoon Yeon , Chajea Jo , Sang-Uk Han
IPC分类号： H01L25/065 , H01L23/00 , H01L23/538
摘要： A semiconductor package includes a first semiconductor chip, a second semiconductor chip on the first semiconductor chip, a first semiconductor structure and a second semiconductor structure that are on the first semiconductor chip and spaced apart from each other across the second semiconductor chip, and a resin-containing member between the second semiconductor chip and the first semiconductor structure and between the second semiconductor chip and the second semiconductor structure. The semiconductor package may be fabricated at a wafer level.
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公开(公告)号：US10978431B2
公开(公告)日：2021-04-13
申请号：US16287249
申请日：2019-02-27
发明人： Jongbo Shim , Ji Hwang Kim , Chajea Jo , Sang-Uk Han
摘要： A semiconductor package includes a lower substrate, a connection substrate coupled to the lower substrate, the connection substrate having a lateral portion surrounding a cavity, and a first conductive pattern on a top surface of the lateral portion, a lower semiconductor chip on the lower substrate, the lower semiconductor chip being in the cavity of the connection substrate, and the lower semiconductor chip including a second conductive pattern on a top surface of the lower semiconductor chip, a bonding member connecting the first conductive pattern and the second conductive pattern to each other, and a top package on the first conductive pattern and the second conductive pattern.
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公开(公告)号：US10361170B2
公开(公告)日：2019-07-23
申请号：US15837187
申请日：2017-12-11
发明人： Sungeun Pyo , Jongbo Shim , Ji Hwang Kim , Chajea Jo , Sang-Uk Han
IPC分类号： H01L23/495 , H01L25/065 , H01L23/538 , H01L21/48 , H01L25/00 , H01L23/00
摘要： A semiconductor package including a first substrate including first upper pads, the first upper pads on a top surface of the first substrate, a second substrate including second upper pads, the second upper pads on a top surface of the second substrate, a pitch of the second upper pads being less than a pitch of the first upper pads, and a first semiconductor chip on and electrically connected to both (i) at least one of the first upper pads and (ii) at least one of the second upper pads may be provided.
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公开(公告)号：US11600545B2
公开(公告)日：2023-03-07
申请号：US17376570
申请日：2021-07-15
发明人： Ji Hwang Kim , Jong Bo Shim , Jang Woo Lee , Yung Cheol Kong , Young Hoon Hyun
IPC分类号： H01L23/367 , H01L23/31 , H01L23/00
摘要： A semiconductor includes a lower structure, an upper structure on the lower structure, and a connection pattern between the lower structure and the upper structure. The connection pattern is configured to electrically connect the lower structure and the upper structure to each other. The lower structure includes a lower base and a first lower chip on the lower base. The first lower chip includes a chip bonding pad, a pad structure, and a heat sink structure. The connection pattern is connected to the upper structure and extends away from the upper structure to be connected to the pad structure. The pad structure has a thickness greater than a thickness of the chip bonding pad. At least a portion of the heat sink structure is at a same height level as at least a portion of the pad structure.
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公开(公告)号：US11069592B2
公开(公告)日：2021-07-20
申请号：US16582418
申请日：2019-09-25
发明人： Ji Hwang Kim , Jong Bo Shim , Jang Woo Lee , Yung Cheol Kong , Young Hoon Hyun
IPC分类号： H01L23/367 , H01L23/31 , H01L23/00
摘要： A semiconductor includes a lower structure, an upper structure on the lower structure, and a connection pattern between the lower structure and the upper structure. The connection pattern is configured to electrically connect the lower structure and the upper structure to each other. The lower structure includes a lower base and a first lower chip on the lower base. The first lower chip includes a chip bonding pad, a pad structure, and a heat sink structure. The connection pattern is connected to the upper structure and extends away from the upper structure to be connected to the pad structure. The pad structure has a thickness greater than a thickness of the chip bonding pad. At least a portion of the heat sink structure is at a same height level as at least a portion of the pad structure.
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公开(公告)号：US20160163608A1
公开(公告)日：2016-06-09
申请号：US14751626
申请日：2015-06-26
发明人： Jin-Woo Park , Ji Hwang Kim , Jongbo Shim
IPC分类号： H01L21/66 , H01L23/498 , H01L23/31
CPC分类号： H01L22/32 , H01L23/3107 , H01L23/3128 , H01L23/3135 , H01L23/3142 , H01L23/49816 , H01L25/065 , H01L2224/06181 , H01L2224/16145 , H01L2224/16225 , H01L2224/17181 , H01L2224/32225 , H01L2224/73204 , H01L2924/15311 , H01L2924/181 , H01L2924/00012 , H01L2924/00
摘要： A semiconductor package includes a package substrate; a semiconductor chip mounted on a top surface of the package substrate; a chip pad disposed on a bottom surface of the semiconductor chip to face the top surface of the package substrate, the chip pad including a connection pad and a measurement pad; and a chip bump including a first bump provided between the package substrate and the connection pad and a second bump provided between the package substrate and the measurement pad. An interconnection disposed within the package substrate is not connected to the second bump to be electrically isolated from the second bump.
摘要翻译： 半导体封装包括封装衬底; 安装在所述封装衬底的顶表面上的半导体芯片; 芯片焊盘，其设置在所述半导体芯片的底面上以面向所述封装基板的上表面，所述芯片焊盘包括连接焊盘和测量焊盘; 以及包括设置在封装基板和连接焊盘之间的第一凸起的芯片凸块和设置在封装基板和测量垫之间的第二凸块。 设置在封装基板内的互连件不与第二凸块连接以与第二凸块电隔离。
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公开(公告)号：US09099541B2
公开(公告)日：2015-08-04
申请号：US14170062
申请日：2014-01-31
发明人： Ji Hwang Kim , Sunpil Youn , Sangwon Kim , Kwang-chul Choi , Tae Hong Min
IPC分类号： H01L21/768 , H01L23/31 , H01L23/36 , H01L23/48 , H01L21/56 , H01L23/498
CPC分类号： H01L21/76898 , H01L21/563 , H01L21/768 , H01L23/3128 , H01L23/3135 , H01L23/36 , H01L23/481 , H01L23/49816 , H01L2224/02372 , H01L2224/0401 , H01L2224/0557 , H01L2224/16146 , H01L2224/16225 , H01L2224/16227 , H01L2224/32225 , H01L2224/73204 , H01L2224/73253 , H01L2225/06568 , H01L2924/00014 , H01L2924/15311 , H01L2924/00 , H01L2224/05552
摘要： A semiconductor device includes a substrate having a first side and a second side such that the first and second sides face each other, a through via plug penetrating the substrate, an insulating film liner, and an antipollution film. The insulating film liner is between the through via plug and the substrate and the insulating film liner has a recessed surface with respect to the second side. The antipollution film covers the second side and the antipollution film is on the recessed surface and between the through via plug and the substrate.
摘要翻译： 半导体器件包括具有第一侧和第二侧的基板，使得第一和第二面彼此面对，贯穿基板的通孔塞，绝缘膜衬垫和防污染膜。 绝缘膜衬垫位于通孔插塞和衬底之间，并且绝缘膜衬套相对于第二侧具有凹陷表面。 防污染膜覆盖第二面，防污染膜位于凹陷表面上，并且在通孔插塞和基底之间。
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公开(公告)号：US12057366B2
公开(公告)日：2024-08-06
申请号：US18178170
申请日：2023-03-03
发明人： Ji Hwang Kim , Jong Bo Shim , Jang Woo Lee , Yung Cheol Kong , Young Hoon Hyun
IPC分类号： H01L23/367 , H01L23/00 , H01L23/31
CPC分类号： H01L23/367 , H01L23/3157 , H01L24/08 , H01L24/48 , H01L2224/02371
摘要： A semiconductor includes a lower structure, an upper structure on the lower structure, and a connection pattern between the lower structure and the upper structure. The connection pattern is configured to electrically connect the lower structure and the upper structure to each other. The lower structure includes a lower base and a first lower chip on the lower base. The first lower chip includes a chip bonding pad, a pad structure, and a heat sink structure. The connection pattern is connected to the upper structure and extends away from the upper structure to be connected to the pad structure. The pad structure has a thickness greater than a thickness of the chip bonding pad. At least a portion of the heat sink structure is at a same height level as at least a portion of the pad structure.
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公开(公告)号：US11908806B2
公开(公告)日：2024-02-20
申请号：US17501008
申请日：2021-10-14
发明人： Dong Ho Kim , Ji Hwang Kim , Hwan Pil Park , Jong Bo Shim
IPC分类号： H01L23/552 , H01L23/498 , H01L21/56 , H01L23/42 , H01L21/48
CPC分类号： H01L23/552 , H01L21/4853 , H01L21/56 , H01L23/42 , H01L23/49816 , H01L23/49822 , H01L23/49838
摘要： A semiconductor package includes a first substrate that includes a first insulating layer, a ground pattern in the first insulating layer, and a first conductive pattern; a first semiconductor chip placed on an upper surface of the first substrate; a ball array structure that is placed on the upper surface of the first substrate along a perimeter of the first semiconductor chip and is electrically connected to the ground pattern; and a shielding structure placed on the upper surface of the first semiconductor chip and in contact with the upper surface of the ball array structure. The ball array structure has a closed loop shape, and includes a solder ball portion and a connecting portion that connects adjacent solder ball portions. A maximum width of the solder ball portion is greater than a width of the connecting portion in a direction perpendicular to an extension direction of the connecting portion.
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10.发明授权公开(公告)号：US10685921B2
公开(公告)日：2020-06-16
申请号：US16198978
申请日：2018-11-23
发明人： Young Kun Jee , Ji Hwang Kim , Un Byoung Kang
摘要： A semiconductor chip module includes a chip package and a printed circuit board (PCB) to which the chip package is mounted. The chip package includes a substrate, a processor disposed in a central region of the substrate, a plurality of active chips disposed around the processor, a plurality of dummy chips disposed in spaces between the plurality of active chips, and an epoxy resin fixing the plurality of active chips and the plurality of dummy chips to the substrate. Channels of the epoxy resin extend between an uppermost surface of a chip body of each of the dummy chips and the substrate of the chip package to control or mitigate warping of the chip package.
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