公开(公告)号：US20240128174A1

公开(公告)日：2024-04-18

申请号：US18380424

申请日：2023-10-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Choongbin Yim ,  Gitae Park ,  Jongbo Shim

IPC: H01L23/498 ,  H01L23/00 ,  H01L23/31 ,  H01L23/367

CPC classification number: H01L23/49816 ,  H01L23/3107 ,  H01L23/3675 ,  H01L23/49822 ,  H01L24/08 ,  H01L24/16 ,  H01L2224/08146 ,  H01L2224/08225 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/182

Abstract: A semiconductor package is provided including: a redistribution substrate having an upper surface and a lower surface, opposite to each other, and including redistribution layers; a semiconductor chip disposed on the upper surface of the redistribution substrate and electrically connected to the redistribution layers; an upper encapsulant encapsulating at least a portion of the semiconductor chip and disposed on the upper surface of the redistribution substrate; a passive component disposed on the lower surface of the redistribution substrate and electrically connected to the redistribution layer; a lower encapsulant encapsulating at least a portion of the passive component and disposed on the lower surface of the redistribution substrate, and having a plurality of openings exposing lowermost redistribution layers among the redistribution layers; and a plurality of bumps respectively disposed within the plurality of openings, the bumps respectively including a first portion in contact with the lowermost redistribution layers and a second portion extending from the first portion and protruding partially downwardly of the plurality of openings.

公开(公告)号：US20240096840A1

公开(公告)日：2024-03-21

申请号：US18370283

申请日：2023-09-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Eunsu Lee ,  Jongbo Shim ,  Sungeun Pyo

IPC: H01L23/00 ,  H01L25/065

CPC classification number: H01L24/32 ,  H01L24/08 ,  H01L24/16 ,  H01L24/73 ,  H01L25/0657 ,  H01L2224/0801 ,  H01L2224/16145 ,  H01L2224/26145 ,  H01L2224/32145 ,  H01L2224/73204 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/1434 ,  H10B80/00

Abstract: A semiconductor device includes a first semiconductor chip. The first semiconductor chip includes a first semiconductor substrate having a first surface and a second surface opposite to the first surface, and having a first active layer adjacent to the first surface, the first semiconductor substrate having a quadrangle shape from a plan view; a first through electrode penetrating at least a portion of the first semiconductor substrate and connected to the first active layer; a second chip connection pad on the second surface of the first semiconductor substrate and connected to the first through electrode; a first dummy pattern positioned outside the second chip connection pad on the second surface of the first semiconductor substrate from the plan view, the first dummy pattern comprising a line pattern extending horizontally along the second surface of the first semiconductor substrate; and a first chip connection pad on the first surface of the first semiconductor substrate and connected to the first through electrode. The first dummy pattern is disposed adjacent to at least one side of four sides of the quadrangle shape of the first semiconductor substrate from the plan view.

公开(公告)号：US20240014191A1

公开(公告)日：2024-01-11

申请号：US18372846

申请日：2023-09-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jeonghyun Lee ,  Jihwang Kim ,  Jongbo Shim

IPC: H01L25/10 ,  H01L23/00 ,  H01L23/498 ,  H01L21/56 ,  H01L23/31

CPC classification number: H01L25/105 ,  H01L24/32 ,  H01L24/16 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49838 ,  H01L21/565 ,  H01L23/3128 ,  H01L23/3142 ,  H01L23/3171 ,  H01L24/73 ,  H01L2225/1058 ,  H01L2924/1431 ,  H01L2924/1436 ,  H01L2924/1437 ,  H01L2924/1438 ,  H01L2924/186 ,  H01L2924/182 ,  H01L2224/73204 ,  H01L2224/16155 ,  H01L2224/32145 ,  H01L2225/1023 ,  H01L2225/1041

Abstract: A semiconductor device having a package on package (PoP) structure, in which a fine pitch between package substrates is implemented, a total height of a package is reduced, and reliability is enhanced. The semiconductor package includes a first package substrate including a first body layer and a first passivation layer, a first semiconductor chip on the first package substrate, a second package substrate on the first package substrate, the second package substrate including a second body layer and a second passivation layer, a first connection member on the first package substrate outside the first semiconductor chip, and a gap filler filled between the first package substrate and the second package substrate, wherein the first package substrate includes a first trench, the second package substrate includes a second trench, and the first semiconductor chip is disposed between the first trench and the second trench.

公开(公告)号：US20230075292A1

公开(公告)日：2023-03-09

申请号：US17986169

申请日：2022-11-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jongbo Shim ,  Jihwang Kim ,  Choongbin Yim

IPC: H01L23/538 ,  H01L23/31 ,  H01L25/10 ,  H01L23/00

Abstract: A semiconductor package comprises a package substrate, a semiconductor chip on the package substrate, and an interposer substrate on the semiconductor chip. The interposer substrate comprises a first surface facing the semiconductor chip and a trench in the first surface, the trench vertically overlapping the semiconductor chip. An insulating filler is provided between the semiconductor chip and the interposer substrate, and at least partially fills the trench of the interposer substrate.

公开(公告)号：US11521934B2

公开(公告)日：2022-12-06

申请号：US17150232

申请日：2021-01-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jongbo Shim ,  Jihwang Kim ,  Choongbin Yim

IPC: H01L23/538 ,  H01L23/31 ,  H01L25/10 ,  H01L23/00

Abstract: A semiconductor package comprises a package substrate, a semiconductor chip on the package substrate, and an interposer substrate on the semiconductor chip. The interposer substrate comprises a first surface facing the semiconductor chip and a trench in the first surface, the trench vertically overlapping the semiconductor chip. An insulating filler is provided between the semiconductor chip and the interposer substrate, and at least partially fills the trench of the interposer substrate.

公开(公告)号：US20160163608A1

公开(公告)日：2016-06-09

申请号：US14751626

申请日：2015-06-26

Applicant: Samsung Electronics Co.,Ltd.

Inventor： Jin-Woo Park ,  Ji Hwang Kim ,  Jongbo Shim

IPC: H01L21/66 ,  H01L23/498 ,  H01L23/31

CPC classification number: H01L22/32 ,  H01L23/3107 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/3142 ,  H01L23/49816 ,  H01L25/065 ,  H01L2224/06181 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/17181 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A semiconductor package includes a package substrate; a semiconductor chip mounted on a top surface of the package substrate; a chip pad disposed on a bottom surface of the semiconductor chip to face the top surface of the package substrate, the chip pad including a connection pad and a measurement pad; and a chip bump including a first bump provided between the package substrate and the connection pad and a second bump provided between the package substrate and the measurement pad. An interconnection disposed within the package substrate is not connected to the second bump to be electrically isolated from the second bump.

Abstract translation: 半导体封装包括封装衬底; 安装在所述封装衬底的顶表面上的半导体芯片; 芯片焊盘，其设置在所述半导体芯片的底面上以面向所述封装基板的上表面，所述芯片焊盘包括连接焊盘和测量焊盘; 以及包括设置在封装基板和连接焊盘之间的第一凸起的芯片凸块和设置在封装基板和测量垫之间的第二凸块。 设置在封装基板内的互连件不与第二凸块连接以与第二凸块电隔离。

公开(公告)号：US11676949B2

公开(公告)日：2023-06-13

申请号：US17370149

申请日：2021-07-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Taeseok Choi ,  Jihwang Kim ,  Jongbo Shim

IPC: H01L25/10 ,  H01L23/498 ,  H01L23/538 ,  H01L23/31

CPC classification number: H01L25/105 ,  H01L23/3128 ,  H01L23/49822 ,  H01L23/49833 ,  H01L23/5383 ,  H01L23/5385 ,  H01L23/5389

Abstract: A semiconductor package includes a lower substrate including a lower passivation layer, a lower pad, element pads and a supporting pad that are disposed on a lower surface of the lower substrate. The lower passivation layer partially covers the lower pad, the element pads and the supporting pad. A semiconductor chip is disposed on an upper surface of the lower substrate. An upper substrate is disposed on the semiconductor chip and is connected to the lower substrate. An encapsulator is disposed between the lower substrate and the upper substrate. An element is disposed on the lower surface of the lower substrate. The element is bonded to the element pads. A lower supporting member is disposed on the lower surface of the lower substrate. A supporting bonding member bonds the lower supporting member to the supporting pad.

公开(公告)号：US20230042622A1

公开(公告)日：2023-02-09

申请号：US17742819

申请日：2022-05-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Choongbin Yim ,  Jihwang Kim ,  Jongbo Shim ,  Jinwoo Park

IPC: H01L23/00 ,  H01L25/10 ,  H01L23/31 ,  H01L23/538 ,  H01L21/48 ,  H01L21/56

Abstract: A semiconductor package includes a first package substrate having a lower surface and an upper surface respectively including a plurality of first lower surface pads and a plurality of first upper surface pads, a second package substrate having a lower surface and an upper surface respectively including a plurality of second lower surface pads and a plurality of second upper surface pads, wherein the plurality of second upper surface pads comprise all of the upper surface pads at the upper surface of the second package substrate, a semiconductor chip provided between the first package substrate and the second package substrate and attached onto the first package substrate, and a plurality of metal core structures connecting some of the plurality of first upper surface pads to some of the plurality of second lower surface pads and not vertically overlapping any of the plurality of second upper surface pads, each metal core structure having a metal core.

公开(公告)号：US20220352110A1

公开(公告)日：2022-11-03

申请号：US17577653

申请日：2022-01-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Choongbin Yim ,  Jihwang Kim ,  Jongbo Shim

IPC: H01L23/00 ,  H01L23/498 ,  H01L25/10

Abstract: A semiconductor package structure includes a package substrate; a semiconductor chip on the package substrate and electrically connected to the package substrate; an interposer substrate above the package substrate and the semiconductor chip, wherein the interposer substrate includes a cavity recessed inward from a lower surface thereof, wherein the semiconductor chip is positioned within the cavity, at least from a plan view; and an adhesive layer positioned inside and outside the cavity, wherein the adhesive layer is formed on all of upper and side surfaces of the semiconductor chip, or on the side surfaces of the semiconductor chip.

公开(公告)号：US11367688B2

公开(公告)日：2022-06-21

申请号：US17090502

申请日：2020-11-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Choongbin Yim ,  Jungwoo Kim ,  Jihwang Kim ,  Jongbo Shim ,  Kyoungsei Choi

IPC: H01L23/538 ,  H01L23/31 ,  H01L23/14

Abstract: A semiconductor package includes a first package substrate, a first semiconductor chip on the first package substrate, a molding layer covering side walls of the first semiconductor chip and including through holes, an interposer on the first semiconductor chip and the molding layer, conductive connectors in the through holes of the molding layer and connected to the first package substrate and the interposer, and an insulating filler including a first portion that fills the through holes of the molding layer so as to surround side walls of the conductive connectors.