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公开(公告)号：US20220216186A1
公开(公告)日：2022-07-07
申请号：US17705872
申请日：2022-03-28
发明人： Sanguk Han , Chajea Jo , Hyoeun Kim , Sunkyoung Seo
IPC分类号： H01L25/065 , H01L23/00 , H01L23/31
摘要： A package-on-package type package includes a lower semiconductor package and an upper semiconductor package. The lower semiconductor package includes a first semiconductor device including a through electrode, a second semiconductor device disposed on the first semiconductor device and including a second through electrode electrically connected to the first through electrode, a first molding member covering a sidewall of at least one of the first semiconductor device and the second semiconductor device, a second molding member covering a sidewall of the first molding member, and an upper redistribution layer disposed on the second semiconductor device and electrically connected to the second through electrode.
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公开(公告)号：US20220139799A1
公开(公告)日：2022-05-05
申请号：US17508483
申请日：2021-10-22
发明人： Jaemin Jung , Sanguk Han , Yoonha Jung
IPC分类号： H01L23/373 , H01L23/498 , H01L25/18 , H05K1/18 , H05K1/02
摘要： A chip-on-film package includes a base film including an upper surface and a lower surface that opposite from each other, a semiconductor chip mounted on the upper surface of the base film, a heat emission layer disposed on the lower surface of the base film to at least partially overlap the semiconductor chip in a thickness direction, an insulating layer disposed on a lower surface of the heat emission layer, and a protective layer surrounding side and lower surfaces of the insulating layer. Accordingly, thermal fatigue of the chip-on-film package may be reduced, and reliability may be increased.
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公开(公告)号：US11842945B2
公开(公告)日：2023-12-12
申请号：US17508483
申请日：2021-10-22
发明人： Jaemin Jung , Sanguk Han , Yoonha Jung
IPC分类号： H01L25/18 , H01L23/373 , H01L23/498 , H05K1/18 , H05K1/02 , H01L23/00 , H05K1/14
CPC分类号： H01L23/3735 , H01L23/3733 , H01L23/3737 , H01L23/4985 , H01L25/18 , H05K1/0204 , H05K1/189 , H01L24/16 , H01L24/73 , H01L2224/16227 , H01L2224/73204 , H05K1/147 , H05K2201/10128
摘要： A chip-on-film package includes a base film including an upper surface and a lower surface that opposite from each other, a semiconductor chip mounted on the upper surface of the base film, a heat emission layer disposed on the lower surface of the base film to at least partially overlap the semiconductor chip in a thickness direction, an insulating layer disposed on a lower surface of the heat emission layer, and a protective layer surrounding side and lower surfaces of the insulating layer. Accordingly, thermal fatigue of the chip-on-film package may be reduced, and reliability may be increased.
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公开(公告)号：US11444060B2
公开(公告)日：2022-09-13
申请号：US16742341
申请日：2020-01-14
发明人： Sanguk Han , Chajea Jo , Hyoeun Kim , Sunkyoung Seo
IPC分类号： H01L25/065 , H01L23/00 , H01L23/31
摘要： A package-on-package type package includes a lower semiconductor package and an upper semiconductor package. The lower semiconductor package includes a first semiconductor device including a through electrode, a second semiconductor device disposed on the first semiconductor device and including a second through electrode electrically connected to the first through electrode, a first molding member covering a sidewall of at least one of the first semiconductor device and the second semiconductor device, a second molding member covering a sidewall of the first molding member, and an upper redistribution layer disposed on the second semiconductor device and electrically connected to the second through electrode.
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公开(公告)号：US11328966B2
公开(公告)日：2022-05-10
申请号：US16749620
申请日：2020-01-22
发明人： Hyoeun Kim , Yonghoe Cho , Sunkyoung Seo , Seunghoon Yeon , Sanguk Han
摘要： A chip-stacked semiconductor package includes a first chip including a first detection pad and a second detection pad; a second chip provided on the first chip, the second chip including a third detection pad facing the first detection pad and a fourth detection pad facing the second detection pad; and a first medium provided between the first detection pad and the third detection pad to connect the first detection pad to the third detection pad through the first medium, and a second medium, different from the first medium, provided between the second detection pad and the fourth detection pad to connect the second detection pad to the fourth detection pad through the second medium.
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公开(公告)号：US12087696B2
公开(公告)日：2024-09-10
申请号：US18095900
申请日：2023-01-11
发明人： Sunkyoung Seo , Taehwan Kim , Hyunjung Song , Hyoeun Kim , Wonil Lee , Sanguk Han
IPC分类号： H01L23/48 , H01L23/00 , H01L23/367 , H01L23/538
CPC分类号： H01L23/5384 , H01L23/367 , H01L23/5385 , H01L23/5386 , H01L24/14
摘要： A semiconductor package includes a package substrate, a lower semiconductor device arranged on the package substrate and including first through electrodes, first lower connection bumps arranged between the package substrate and the lower semiconductor device and electrically connecting the package substrate to the first through electrodes, a connecting substrate arranged on the package substrate and including second through electrodes, second lower connection bumps arranged between the package substrate and the connecting substrate and electrically connecting the package substrate to the second through electrodes, and an upper semiconductor device arranged on the lower semiconductor device and electrically connected to the first through electrodes and the second through electrodes.
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公开(公告)号：US11923342B2
公开(公告)日：2024-03-05
申请号：US17705872
申请日：2022-03-28
发明人： Sanguk Han , Chajea Jo , Hyoeun Kim , Sunkyoung Seo
IPC分类号： H01L25/065 , H01L23/00 , H01L23/31
CPC分类号： H01L25/0657 , H01L23/3121 , H01L23/3135 , H01L24/13
摘要： A package-on-package type package includes a lower semiconductor package and an upper semiconductor package. The lower semiconductor package includes a first semiconductor device including a through electrode, a second semiconductor device disposed on the first semiconductor device and including a second through electrode electrically connected to the first through electrode, a first molding member covering a sidewall of at least one of the first semiconductor device and the second semiconductor device, a second molding member covering a sidewall of the first molding member, and an upper redistribution layer disposed on the second semiconductor device and electrically connected to the second through electrode.
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公开(公告)号：US11574873B2
公开(公告)日：2023-02-07
申请号：US17003639
申请日：2020-08-26
发明人： Sunkyoung Seo , Taehwan Kim , Hyunjung Song , Hyoeun Kim , Wonil Lee , Sanguk Han
IPC分类号： H01L23/367 , H01L23/538 , H01L23/00
摘要： A semiconductor package includes a package substrate, a lower semiconductor device arranged on the package substrate and including first through electrodes, first lower connection bumps arranged between the package substrate and the lower semiconductor device and electrically connecting the package substrate to the first through electrodes, a connecting substrate arranged on the package substrate and including second through electrodes, second lower connection bumps arranged between the package substrate and the connecting substrate and electrically connecting the package substrate to the second through electrodes, and an upper semiconductor device arranged on the lower semiconductor device and electrically connected to the first through electrodes and the second through electrodes.
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公开(公告)号：US20240142493A1
公开(公告)日：2024-05-02
申请号：US18497401
申请日：2023-10-30
发明人： Sanguk Han , Jaekul Lee , Hyungsun Jang , Taehun Kim
CPC分类号： G01R1/0466 , G01R31/2863 , H01L24/13 , H01L24/29 , H01L2224/13006 , H01L2224/29022
摘要： A socket for testing a semiconductor package includes a body having an internal space configured to accommodate a semiconductor package; and at least a first spacer on the body and positioned to contact a first surface of the semiconductor package when the semiconductor package is placed on the body. The body includes a lower socket portion provided with through-holes, configured through which to receive meter reading pins that contact external connection terminals of the semiconductor package, and an upper socket portion disposed above the lower socket portion, and the first spacer is disposed on a surface of the lower socket portion that faces the first surface of the semiconductor package when the semiconductor package is placed on the body.
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公开(公告)号：US11869818B2
公开(公告)日：2024-01-09
申请号：US17733411
申请日：2022-04-29
发明人： Hyoeun Kim , Yonghoe Cho , Sunkyoung Seo , Seunghoon Yeon , Sanguk Han
CPC分类号： H01L22/32 , G01R27/2605 , G01R31/2818 , H01L22/14 , H01L23/3128 , H01L24/94 , H01L25/0657 , H01L25/50 , H01L2225/06513
摘要： A chip-stacked semiconductor package includes a first chip including a first detection pad and a second detection pad; a second chip provided on the first chip, the second chip including a third detection pad facing the first detection pad and a fourth detection pad facing the second detection pad; and a first medium provided between the first detection pad and the third detection pad to connect the first detection pad to the third detection pad through the first medium, and a second medium, different from the first medium, provided between the second detection pad and the fourth detection pad to connect the second detection pad to the fourth detection pad through the second medium.
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