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公开(公告)号：US20210351122A1
公开(公告)日：2021-11-11
申请号：US17105736
申请日：2020-11-27
发明人： Bong-Soo Kim , Juhyeon Kim
IPC分类号： H01L23/522 , H01L23/31 , H01L23/528
摘要： Provided is a semiconductor package including a redistribution substrate, a connection substrate on the redistribution substrate, the connection substrate having an opening that penetrates the connection substrate, a semiconductor chip in the opening of the connection substrate, and a molding layer that covers the semiconductor chip and the connection substrate, and fills a space between the semiconductor chip and the connection substrate, the connection substrate includes a base layer, a plurality of vias that vertically penetrate the base layer, a plurality of first patterns on a top surface of the base layer and connected to the plurality of vias, and a plurality of second patterns on a bottom surface of the base layer and connected to the plurality of vias, an extension of the molding layer extends into a plurality of holes that are spaced apart from the plurality of vias and are formed to vertically penetrate the base layer.
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公开(公告)号：US12021073B2
公开(公告)日：2024-06-25
申请号：US17656011
申请日：2022-03-23
发明人： Juhyeon Kim , Hyoeun Kim , Sunkyoung Seo
IPC分类号： H01L21/768 , H01L21/78 , H01L23/00 , H01L25/00 , H01L25/065
CPC分类号： H01L25/50 , H01L21/76898 , H01L21/78 , H01L24/03 , H01L24/80 , H01L24/94 , H01L24/97 , H01L24/08 , H01L24/13 , H01L25/0657 , H01L2224/0401 , H01L2224/08146 , H01L2224/80001 , H01L2225/06541
摘要： A method of manufacturing a semiconductor package includes preparing a wafer structure having a first semiconductor substrate and a plurality of first front surface connection pads. A lower semiconductor chip having a preliminary semiconductor substrate and a plurality of second front surface connection pads are attached to the wafer structure such that the plurality of first front surface connection pads and the plurality of second front surface connection pads correspond to each other. A plurality of bonding pads is formed by bonding together the plurality of first front surface connection pads and the plurality of second front surface connection pads corresponding to each other. A second semiconductor substrate having a horizontal width that is less than that of the second wiring structure is formed by removing a portion of the preliminary semiconductor substrate.
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公开(公告)号：US20230119548A1
公开(公告)日：2023-04-20
申请号：US17873990
申请日：2022-07-26
发明人： Hyoeun Kim , Juhyeon Kim , Wonil Lee , Youngkun Jee
IPC分类号： H01L23/00 , H01L25/065
摘要： A semiconductor package includes a first semiconductor chip including a first substrate and a first bonding layer disposed on the first substrate, and having a flat first outer surface provided by the first bonding layer; and a second semiconductor chip disposed on the first outer surface of the first semiconductor chip, including a second substrate and a second bonding layer disposed on the second substrate, and having a flat second outer surface provided by the second bonding layer and contacting the first outer surface of the first semiconductor chip. The first bonding layer includes a first outermost insulating layer providing the first outer surface, a first internal insulating layer stacked between the first outermost insulating layer and the first substrate, first external marks disposed in the first outermost insulating layer and spaced apart from each other, and first internal marks interlaced with the first external marks within the first internal insulating layer.
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公开(公告)号：US20240006272A1
公开(公告)日：2024-01-04
申请号：US18296056
申请日：2023-04-05
发明人： Juhyeon Kim , Ilhwan Kim , Sunkyoung Seo , Chajea Jo
IPC分类号： H01L23/48 , H01L25/065 , H01L23/00 , H01L23/498 , H01L23/31 , H01L21/56 , H01L23/532
CPC分类号： H01L23/481 , H01L25/0657 , H01L24/16 , H01L23/49822 , H01L23/3128 , H01L21/565 , H01L24/05 , H01L24/32 , H01L24/73 , H01L23/5329 , H01L23/49838 , H01L2225/06513 , H01L2224/16235 , H01L2224/0557 , H01L2224/73203 , H01L2224/32225
摘要： A semiconductor package includes: a first semiconductor chip including first pads; a second semiconductor chip below the first semiconductor chip, the second semiconductor chip including a substrate including a front surface and an opposing rear surface, second pads on the front surface and in contact with the first pads, and through-electrodes electrically connected to the second pads and including protruding portions protruding from the rear surface of the substrate; through-via structures disposed around the second semiconductor chip and in contact with the first pads; a first dielectric layer extending along the rear surface of the substrate and side surfaces of the protruding portions of the through-electrodes; a second dielectric layer below the first dielectric layer and in a space between the protruding portions of the through-electrodes and between the through-via structures; and bump structures below the second dielectric layer and electrically connected to the through-electrodes and the through-via structures.
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公开(公告)号：US20230118535A1
公开(公告)日：2023-04-20
申请号：US17836142
申请日：2022-06-09
发明人： Juhyeon Kim , Hyoeun Kim , Sunkyoung Seo
IPC分类号： H01L25/065 , H01L23/544 , H01L23/528 , H01L23/48 , H01L23/498 , H01L23/00 , H01L23/31
摘要： A semiconductor package may include a redistribution substrate, a first semiconductor chip on the redistribution substrate, and a second semiconductor chip between the redistribution substrate and the first semiconductor chip. The second semiconductor chip may have a width in a first direction that is smaller than a width of the first semiconductor chip in the first direction. The first semiconductor chip may include a first alignment key pattern on a bottom surface thereof. The second semiconductor chip may be spaced apart from the first alignment key pattern. The second semiconductor chip may include a second interconnection layer on the bottom surface of the first semiconductor chip, a second semiconductor substrate on a bottom surface of the second interconnection layer and exposing a bottom surface of an edge region of the second interconnection layer, and a second alignment key pattern on the edge region of the second interconnection layer.
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公开(公告)号：US20240321857A1
公开(公告)日：2024-09-26
申请号：US18736766
申请日：2024-06-07
发明人： Juhyeon Kim , Hyoeun Kim , Sunkyoung Seo
IPC分类号： H01L25/00 , H01L21/768 , H01L21/78 , H01L23/00 , H01L25/065
CPC分类号： H01L25/50 , H01L21/76898 , H01L21/78 , H01L24/03 , H01L24/80 , H01L24/94 , H01L24/97 , H01L24/08 , H01L24/13 , H01L25/0657 , H01L2224/0401 , H01L2224/08146 , H01L2224/80001 , H01L2225/06541
摘要： A method of manufacturing a semiconductor package includes preparing a wafer structure having a first semiconductor substrate and a plurality of first front surface connection pads. A lower semiconductor chip having a preliminary semiconductor substrate and a plurality of second front surface connection pads are attached to the wafer structure such that the plurality of first front surface connection pads and the plurality of second front surface connection pads correspond to each other. A plurality of bonding pads is formed by bonding together the plurality of first front surface connection pads and the plurality of second front surface connection pads corresponding to each other. A second semiconductor substrate having a horizontal width that is less than that of the second wiring structure is formed by removing a portion of the preliminary semiconductor substrate.
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公开(公告)号：US20240055406A1
公开(公告)日：2024-02-15
申请号：US18364802
申请日：2023-08-03
发明人： Yeongseon Kim , Dohyun Kim , Juhyeon Kim , Hyoeun Kim , Seonkyung Seo , Chajea Jo
IPC分类号： H01L25/065 , H01L25/10 , H01L23/31 , H01L23/00
CPC分类号： H01L25/0657 , H01L25/105 , H01L23/3107 , H01L24/03 , H01L24/05 , H01L24/08 , H01L24/80 , H01L2225/06541 , H01L2225/06565 , H01L2224/0384 , H01L2224/039 , H01L2224/05014 , H01L2224/05015 , H01L2224/05541 , H01L2224/05554 , H01L2224/05555 , H01L2224/08121 , H01L2224/08148 , H01L2224/08235 , H01L2224/80203 , H01L2224/80895 , H01L2224/80896 , H01L2924/1431 , H01L2924/1434 , H01L2924/38
摘要： A semiconductor package includes a first semiconductor chip including a first semiconductor device, a second semiconductor chip including a second semiconductor device, and a bonding structure between the first and second semiconductor chips, the bonding structure including a first bonding pad, a first bonding insulating layer, a second bonding pad in contact with the first bonding pad, and a second bonding insulating layer in contact with the first bonding insulating layer. The first bonding pad may include a first pad metal layer and a first conductive barrier layer surrounding the first pad metal layer, and the first conductive barrier layer may include a horizontal extension portion extending on an edge of an upper surface of the first pad metal layer.
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公开(公告)号：US20230013176A1
公开(公告)日：2023-01-19
申请号：US17656011
申请日：2022-03-23
发明人： Juhyeon Kim , Hyoeun Kim , Sunkyoung Seo
IPC分类号： H01L25/00 , H01L23/00 , H01L21/768 , H01L21/78
摘要： A method of manufacturing a semiconductor package includes preparing a wafer structure having a first semiconductor substrate and a plurality of first front surface connection pads. A lower semiconductor chip having a preliminary semiconductor substrate and a plurality of second front surface connection pads are attached to the wafer structure such that the plurality of first front surface connection pads and the plurality of second front surface connection pads correspond to each other. A plurality of bonding pads is formed by bonding together the plurality of first front surface connection pads and the plurality of second front surface connection pads corresponding to each other. A second semiconductor substrate having a horizontal width that is less than that of the second wiring structure is formed by removing a portion of the preliminary semiconductor substrate.
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公开(公告)号：US11417597B2
公开(公告)日：2022-08-16
申请号：US17105736
申请日：2020-11-27
发明人： Bong-Soo Kim , Juhyeon Kim
IPC分类号： H01L23/522 , H01L23/528 , H01L23/31
摘要： Provided is a semiconductor package including a redistribution substrate, a connection substrate on the redistribution substrate, the connection substrate having an opening that penetrates the connection substrate, a semiconductor chip in the opening of the connection substrate, and a molding layer that covers the semiconductor chip and the connection substrate, and fills a space between the semiconductor chip and the connection substrate, the connection substrate includes a base layer, a plurality of vias that vertically penetrate the base layer, a plurality of first patterns on a top surface of the base layer and connected to the plurality of vias, and a plurality of second patterns on a bottom surface of the base layer and connected to the plurality of vias, an extension of the molding layer extends into a plurality of holes that are spaced apart from the plurality of vias and are formed to vertically penetrate the base layer.
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