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1.
公开(公告)号:US20190067163A1
公开(公告)日:2019-02-28
申请号:US16102117
申请日:2018-08-13
申请人: Intel IP Corporation
发明人: Quan Qi , Carlton E. Hanna , Eytan Mann , Sidharth Dalmia
IPC分类号: H01L23/433 , H01L23/367 , H01L21/48 , H01L23/538 , H01L23/498 , H01L23/00
CPC分类号: H01L23/4334 , H01L21/4814 , H01L23/13 , H01L23/3128 , H01L23/3677 , H01L23/49816 , H01L23/5389 , H01L23/552 , H01L23/66 , H01L24/13 , H01L24/16 , H01L24/19 , H01L24/96 , H01L2223/6677 , H01L2224/13101 , H01L2224/16225 , H01L2924/1432 , H01L2924/1434 , H01L2924/15153 , H01L2924/15311 , H01L2924/38 , H01L2924/014 , H01L2924/00014
摘要: Methods of forming microelectronic package structures/modules, and structures formed thereby, are described. Structures included herein may include a die on a first substrate, at least one first component adjacent the die on the first substrate, and molding material on the first substrate, wherein the at least one component and the die are embedded in the molding material. A second substrate may be physically coupled to the first substrate. A communication structure may be disposed on a top surface of the second substrate, wherein at least one second component may also be located on the top surface of the second substrate.
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公开(公告)号:US20230170322A1
公开(公告)日:2023-06-01
申请号:US17536498
申请日:2021-11-29
IPC分类号: H01L23/00 , H01L25/065 , H01L23/495
CPC分类号: H01L24/37 , H01L24/32 , H01L24/38 , H01L25/0657 , H01L23/49575 , H01L2224/32245 , H01L2224/3702 , H01L2924/38
摘要: An integrated circuit package includes a lead frame, a first die adhered to the lead frame on a first side of the first die, and a first clip having a clip foot adhered to the lead frame. The first clip has a first side and a second side. A first die attachment region is defined by a first group of four notches in the first side of the first clip. The first clip extends from the lead frame and contacts a second side of the first die at the first die attachment region via a first layer of solder paste. The integrated circuit package further has a second die adhered to the second side of the first clip on a first side of the second die, and a second clip having a clip foot adhered to the lead frame. The second clip has a first side and a second side. A second die attachment region is defined by a second group of four notches in the first side of the second clip. The second clip extends from the lead frame and contacts a second side of the second die at the second die attachment region via a second layer of solder paste.
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公开(公告)号:US09661756B1
公开(公告)日:2017-05-23
申请号:US14455642
申请日:2014-08-08
申请人: Flextronics AP, LLC
发明人: Jennifer Nguyen , David Geiger , Anwar Mohammed , Murad Kurwa
CPC分类号: H05K3/244 , G06K19/07754 , H01L23/5386 , H01L24/65 , H01L25/00 , H01L2924/38 , H01M6/40 , H04B1/3816 , H05K1/097 , H05K1/111 , H05K3/30 , H05K3/40
摘要: Embodiments of the present invention relate to nano-copper pillar interconnects. Nano-copper material is a mixture of nano-copper particles and one or more organic fluxes. In some embodiments, the one or more organic fluxes include organic solvents that help bind the nano-copper particles together and allow the nano-copper material to be printable. The nano-copper material is applied onto bond pads on a printed circuit board (PCB) via a printing process, a dipping process or the like, to form nano-copper covered PCB bond pads. A component can thereafter be coupled with the PCB at the nano-copper covered PCB bond pads. What is left when the solvents evaporate are nano-copper pillar interconnects that form, coupling the component with the PCB bond pads. The nano-copper pillar interconnects are of pure copper.
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4.
公开(公告)号:US09397065B1
公开(公告)日:2016-07-19
申请号:US14468216
申请日:2014-08-25
申请人: Flextronics AP, LLC
发明人: Jennifer Nguyen , David Geiger , Ranilo Aranda , Jonas Sjoberg , Anwar Mohammed , Murad Kurwa
IPC分类号: H01L23/544 , H01L23/00 , H01L25/00 , H01L23/538
CPC分类号: H05K3/244 , G06K19/07754 , H01L23/5386 , H01L24/65 , H01L25/00 , H01L2924/38 , H01M6/40 , H04B1/3816 , H05K1/097 , H05K1/111 , H05K3/30 , H05K3/40
摘要: Embodiments of the present invention relate to a fixture design for pre-attachment package on package component assembly. The fixture design includes a plurality of pockets arranged in a N×M array. The plurality of pockets is sized to receive bottom packages. The fixture design includes global fiducials that are used to locate positions of the pockets on the fixture, and sets of local fiducials, with each set being specific to one of the pockets and used to refine the position of the location of a corresponding pocket. Each of the pockets can include one or more ear cuts for easy component placement and component removal. The fixture design can include a vacuum port for coupling with a vacuum source for drawing a vacuum to hold the bottom packages down. The fixture design can also include a cover that is used with the fixture to keep the components from being disturbed.
摘要翻译: 本发明的实施例涉及一种用于包装部件组件上的预附接包装的夹具设计。 夹具设计包括以N×M阵列排列的多个口袋。 多个口袋的尺寸适于接纳底部包装。 夹具设计包括用于定位夹具上的凹穴的位置的全局基准和局部基准的集合,其中每一组特定于其中一个凹穴并且用于细化相应凹穴的位置的位置。 每个口袋可以包括一个或多个耳朵切口,便于元件放置和元件移除。 夹具设计可以包括用于与真空源耦合的真空端口,用于抽真空以将底部包装件向下保持。 夹具设计还可以包括与夹具一起使用以防止部件受到干扰的盖子。
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5.
公开(公告)号:US20240363562A1
公开(公告)日:2024-10-31
申请号:US18764147
申请日:2024-07-03
发明人: Dongdong Shao
CPC分类号: H01L24/05 , H01L23/3185 , H01L24/03 , H01L2224/03462 , H01L2224/03632 , H01L2224/0384 , H01L2224/05567 , H01L2924/38
摘要: The present invention discloses a packaging structure for large-size chips adapted to small-size packages and a processing method thereof, wherein the first solder pad cavity and the second solder pad cavity are intersected and misaligned; the channel is located on one side of the two solder pad cavities, with the inner wall of the channel being a metallized hole wall; by providing a channel with a metallized hole wall on the proximal side of the packaging structure, more space is provided for chips, which meets the processing needs for large-size chips adapted to small-size packages.
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公开(公告)号:US09502327B2
公开(公告)日:2016-11-22
申请号:US14913719
申请日:2015-01-09
申请人: DENSO CORPORATION
发明人: Shun Sugiura , Yasushi Ookura
IPC分类号: H01L23/367 , B23K3/08 , H01L23/00 , B23K1/00 , B23K1/008 , H01L23/433 , H01L23/495
CPC分类号: H01L23/3675 , B23K1/0016 , B23K1/008 , B23K3/087 , B23K2101/40 , H01L23/4334 , H01L23/49513 , H01L23/49562 , H01L23/49575 , H01L24/29 , H01L24/32 , H01L24/33 , H01L24/48 , H01L24/73 , H01L24/83 , H01L24/85 , H01L24/92 , H01L2224/05554 , H01L2224/29101 , H01L2224/32245 , H01L2224/33181 , H01L2224/48091 , H01L2224/48247 , H01L2224/48472 , H01L2224/73265 , H01L2224/83192 , H01L2224/83201 , H01L2224/83203 , H01L2224/83815 , H01L2224/83986 , H01L2224/85205 , H01L2224/92247 , H01L2924/00014 , H01L2924/13055 , H01L2924/181 , H01L2924/38 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207 , H01L2924/014
摘要: A semiconductor device includes: a semiconductor element having a solder region and a non-solder region on a first face; a first metal member disposed on the first face of the semiconductor element; a second metal member disposed on a rear face of the semiconductor element; a first solder that connects the solder region of the semiconductor element and the first metal member; and a second solder that connects the rear face of the semiconductor element and the second metal member. At least the second solder provides a melt-bond. A gravity center position of the first metal member coincides with a center position of the semiconductor element in a projection view from a stacking direction.
摘要翻译: 半导体器件包括:在第一面上具有焊料区域和非焊接区域的半导体元件; 设置在所述半导体元件的第一面上的第一金属构件; 设置在所述半导体元件的背面上的第二金属构件; 连接半导体元件的焊料区域和第一金属部件的第一焊料; 以及连接半导体元件的后表面和第二金属构件的第二焊料。 至少第二焊料提供熔融粘合。 第一金属构件的重心位置与半导体元件的从堆叠方向的投影视图的中心位置重合。
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公开(公告)号:US09053405B1
公开(公告)日:2015-06-09
申请号:US14162483
申请日:2014-01-23
申请人: Flextronics AP, LLC
发明人: Weifeng Liu , Anwar Mohammed , Murad Kurwa
IPC分类号: G06K19/07 , G06K19/077 , H01M6/40
CPC分类号: H05K3/244 , G06K19/07754 , H01L23/5386 , H01L24/65 , H01L25/00 , H01L2924/38 , H01M6/40 , H04B1/3816 , H05K1/097 , H05K1/111 , H05K3/30 , H05K3/40
摘要: A printed circuit including a non-conductive substrate, a first conductive layer printed on the non-conductive substrate and one or more additional layers printed on the substrate. The first conductive layer is able to have one or more antennas each forming a predetermined pattern, a first conductive sheet and one or more conductive traces. The one or more additional layers include a first electrode printed on the top of the first conductive sheet, a buffer printed on top of the first electrode, a second electrode printed on top of the buffer and a second conductive sheet printed on top of the second electrode. The printed circuit is further able to include an RFID chip electrically coupled with the antennas and at least one of the first and second conductive sheets via the conductive traces, wherein the first and second conductive sheets, the buffer and the first and second electrodes form a power source that provides electrical power to the RFID chip.
摘要翻译: 一种印刷电路,包括非导电衬底,印刷在非导电衬底上的第一导电层和印刷在衬底上的一个或多个附加层。 第一导电层能够具有各自形成预定图案的一个或多个天线,第一导电片和一个或多个导电迹线。 所述一个或多个附加层包括印刷在第一导电片的顶部上的第一电极,印刷在第一电极顶部上的缓冲器,印刷在缓冲器顶部的第二电极和印刷在第二导电片的第二个顶部上的第二导电片 电极。 印刷电路还能够包括通过导电迹线与天线以及第一和第二导电片中的至少一个电耦合的RFID芯片,其中第一和第二导电片,缓冲器和第一和第二电极形成 向RFID芯片提供电力的电源。
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公开(公告)号:US20240055406A1
公开(公告)日:2024-02-15
申请号:US18364802
申请日:2023-08-03
发明人: Yeongseon Kim , Dohyun Kim , Juhyeon Kim , Hyoeun Kim , Seonkyung Seo , Chajea Jo
IPC分类号: H01L25/065 , H01L25/10 , H01L23/31 , H01L23/00
CPC分类号: H01L25/0657 , H01L25/105 , H01L23/3107 , H01L24/03 , H01L24/05 , H01L24/08 , H01L24/80 , H01L2225/06541 , H01L2225/06565 , H01L2224/0384 , H01L2224/039 , H01L2224/05014 , H01L2224/05015 , H01L2224/05541 , H01L2224/05554 , H01L2224/05555 , H01L2224/08121 , H01L2224/08148 , H01L2224/08235 , H01L2224/80203 , H01L2224/80895 , H01L2224/80896 , H01L2924/1431 , H01L2924/1434 , H01L2924/38
摘要: A semiconductor package includes a first semiconductor chip including a first semiconductor device, a second semiconductor chip including a second semiconductor device, and a bonding structure between the first and second semiconductor chips, the bonding structure including a first bonding pad, a first bonding insulating layer, a second bonding pad in contact with the first bonding pad, and a second bonding insulating layer in contact with the first bonding insulating layer. The first bonding pad may include a first pad metal layer and a first conductive barrier layer surrounding the first pad metal layer, and the first conductive barrier layer may include a horizontal extension portion extending on an edge of an upper surface of the first pad metal layer.
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公开(公告)号:US20180019199A1
公开(公告)日:2018-01-18
申请号:US15644403
申请日:2017-07-07
发明人: Ming Xiao , Zeqiang Yao , Heng Li , Fayou Yin
IPC分类号: H01L23/498 , H01L21/311 , H01L21/768 , H01L21/56 , H01L21/02 , H01L23/31 , H01L23/00 , H01L21/48
CPC分类号: H01L23/49838 , H01L21/02271 , H01L21/31111 , H01L21/486 , H01L21/56 , H01L21/76871 , H01L23/3171 , H01L23/3192 , H01L23/49827 , H01L24/03 , H01L24/05 , H01L24/11 , H01L24/13 , H01L2224/02381 , H01L2224/0239 , H01L2224/03462 , H01L2224/0347 , H01L2224/0391 , H01L2224/0401 , H01L2224/05096 , H01L2224/05124 , H01L2224/05548 , H01L2224/05567 , H01L2224/05647 , H01L2224/11462 , H01L2224/1147 , H01L2224/11849 , H01L2224/13005 , H01L2224/13024 , H01L2224/13082 , H01L2224/13111 , H01L2224/13147 , H01L2224/13611 , H01L2924/38 , H01L2924/014 , H01L2924/206 , H01L2924/00014
摘要: A semiconductor device having a first dielectric layer and a redistribution layer. The redistribution layer has sidewalls and is formed on a passivation layer of the semiconductor device. The first dielectric layer covers the sidewalls of the redistribution layer. The first dielectric layer is insulative and has a physical property of stopping the migration of the redistribution layer.
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公开(公告)号:US20160204047A1
公开(公告)日:2016-07-14
申请号:US14913719
申请日:2015-01-09
申请人: DENSO CORPORATION
发明人: Shun SUGIURA , Yasushi OOKURA
IPC分类号: H01L23/367 , B23K1/00 , H01L23/00
CPC分类号: H01L23/3675 , B23K1/0016 , B23K1/008 , B23K3/087 , B23K2101/40 , H01L23/4334 , H01L23/49513 , H01L23/49562 , H01L23/49575 , H01L24/29 , H01L24/32 , H01L24/33 , H01L24/48 , H01L24/73 , H01L24/83 , H01L24/85 , H01L24/92 , H01L2224/05554 , H01L2224/29101 , H01L2224/32245 , H01L2224/33181 , H01L2224/48091 , H01L2224/48247 , H01L2224/48472 , H01L2224/73265 , H01L2224/83192 , H01L2224/83201 , H01L2224/83203 , H01L2224/83815 , H01L2224/83986 , H01L2224/85205 , H01L2224/92247 , H01L2924/00014 , H01L2924/13055 , H01L2924/181 , H01L2924/38 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207 , H01L2924/014
摘要: A semiconductor device includes: a semiconductor element having a solder region and a non-solder region on a first face; a first metal member disposed on the first face of the semiconductor element; a second metal member disposed on a rear face of the semiconductor element; a first solder that connects the solder region of the semiconductor element and the first metal member; and a second solder that connects the rear face of the semiconductor element and the second metal member. At least the second solder provides a melt-bond. A gravity center position of the first metal member coincides with a center position of the semiconductor element in a projection view from a stacking direction.
摘要翻译: 半导体器件包括:在第一面上具有焊料区域和非焊接区域的半导体元件; 设置在所述半导体元件的第一面上的第一金属构件; 设置在所述半导体元件的背面上的第二金属构件; 连接半导体元件的焊料区域和第一金属部件的第一焊料; 以及连接半导体元件的后表面和第二金属构件的第二焊料。 至少第二焊料提供熔融粘合。 第一金属构件的重心位置与半导体元件的从堆叠方向的投影视图的中心位置重合。
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