公开(公告)号：US20170033071A1

公开(公告)日：2017-02-02

申请号：US15202700

申请日：2016-07-06

Applicant: SHINKO ELECTRIC INDUSTRIES CO., LTD.

Inventor： Sumihiro ICHIKAWA

IPC: H01L23/00 ,  H01L23/498 ,  H01L23/29 ,  H01L25/065 ,  H01L23/31

CPC classification number: H01L24/17 ,  H01L23/295 ,  H01L23/3142 ,  H01L23/49811 ,  H01L23/49833 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L24/94 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/036 ,  H01L2224/0401 ,  H01L2224/111 ,  H01L2224/1132 ,  H01L2224/11334 ,  H01L2224/1147 ,  H01L2224/1184 ,  H01L2224/11845 ,  H01L2224/11848 ,  H01L2224/119 ,  H01L2224/13005 ,  H01L2224/13014 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/1319 ,  H01L2224/1403 ,  H01L2224/14051 ,  H01L2224/14131 ,  H01L2224/14136 ,  H01L2224/14179 ,  H01L2224/14505 ,  H01L2224/16145 ,  H01L2224/16148 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/2929 ,  H01L2224/29387 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81065 ,  H01L2224/81143 ,  H01L2224/81193 ,  H01L2224/81856 ,  H01L2224/81862 ,  H01L2224/81895 ,  H01L2224/81907 ,  H01L2224/81986 ,  H01L2224/83104 ,  H01L2224/83862 ,  H01L2224/92125 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06565 ,  H01L2225/06593 ,  H01L2924/00015 ,  H01L2924/14 ,  H05K3/305 ,  H05K3/328 ,  H05K3/368 ,  H01L2224/81121 ,  H01L2224/81 ,  H01L2924/00014 ,  H01L2924/0665 ,  H01L2924/05442 ,  H01L2224/034 ,  H01L2224/113 ,  H01L2924/00012 ,  H01L2224/81203 ,  H01L2924/00

Abstract: A packaging structure includes a first substrate including a first metal terminal and a first protruding resin portion formed at a first surface; a second substrate including a second metal terminal and a second protruding resin portion formed at a second surface, the second metal terminal being made of the same kind of metal as the first metal terminal; and a sealing portion filled between the first surface of the first substrate and the second surface of the second substrate, the first metal terminal and the second metal terminal being directly bonded with each other, the first protruding resin portion and the second protruding resin portion being directly bonded with each other, each of the first protruding resin portion and the second protruding resin portion being made of a resin material that does not include fillers, and the sealing portion being made of a resin material including fillers.

Abstract translation: 包装结构包括：第一基板，包括形成在第一表面的第一金属端子和第一突出树脂部分; 第二基板，包括形成在第二表面的第二金属端子和第二突出树脂部分，所述第二金属端子由与所述第一金属端子相同种类的金属制成; 以及填充在第一基板的第一表面和第二基板的第二表面之间的密封部分，第一金属端子和第二金属端子彼此直接接合，第一突出树脂部分和第二突出树脂部分是 彼此直接接合，第一突出树脂部分和第二突出树脂部分由不包括填料的树脂材料制成，并且密封部分由包括填料的树脂材料制成。

公开(公告)号：US20170025387A1

公开(公告)日：2017-01-26

申请号：US15196170

申请日：2016-06-29

Applicant: SHINKO ELECTRIC INDUSTRIES CO., LTD.

Inventor： Sumihiro ICHIKAWA

IPC: H01L25/065 ,  H01L25/00 ,  H01L23/00

CPC classification number: H01L25/0657 ,  H01L23/49811 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L24/29 ,  H01L24/32 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L24/94 ,  H01L24/97 ,  H01L25/50 ,  H01L2224/036 ,  H01L2224/0401 ,  H01L2224/1132 ,  H01L2224/11334 ,  H01L2224/11462 ,  H01L2224/1147 ,  H01L2224/1184 ,  H01L2224/11845 ,  H01L2224/119 ,  H01L2224/13014 ,  H01L2224/13082 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/1403 ,  H01L2224/14051 ,  H01L2224/14131 ,  H01L2224/14136 ,  H01L2224/14179 ,  H01L2224/14505 ,  H01L2224/16145 ,  H01L2224/16148 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/1701 ,  H01L2224/2929 ,  H01L2224/29387 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81065 ,  H01L2224/81143 ,  H01L2224/81193 ,  H01L2224/812 ,  H01L2224/81205 ,  H01L2224/81815 ,  H01L2224/81895 ,  H01L2224/81906 ,  H01L2224/81907 ,  H01L2224/81986 ,  H01L2224/83104 ,  H01L2224/83862 ,  H01L2224/83895 ,  H01L2224/92125 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06565 ,  H01L2225/06593 ,  H01L2924/00015 ,  H01L2924/14 ,  H05K3/328 ,  H05K3/368 ,  H05K3/4007 ,  H05K2203/167 ,  H01L2924/00012 ,  H01L2924/01083 ,  H01L2924/0103 ,  H01L2924/00014 ,  H01L2224/81121 ,  H01L2224/81 ,  H01L2924/0665 ,  H01L2924/05442 ,  H01L2224/034 ,  H01L2224/113 ,  H01L2224/81203 ,  H01L2224/81201 ,  H01L2924/00

Abstract: A packaging structure includes a first substrate including a first metal terminal and a second metal terminal whose height is lower than the height of the first metal terminal; and a second substrate including a third metal terminal and a fourth metal terminal whose height is lower than the height of the third metal terminal, the second substrate being provided on the first substrate, the first metal terminal and the third metal terminal being directly bonded with each other, and the second metal terminal and the fourth metal terminal being bonded via a connection portion.

Abstract translation: 包装结构包括：第一基板，包括第一金属端子和第二金属端子，第二金属端子的高度低于第一金属端子的高度; 以及第二基板，包括高度低于所述第三金属端子的高度的第三金属端子和第四金属端子，所述第二基板设置在所述第一基板上，所述第一金属端子和所述第三金属端子直接与 并且第二金属端子和第四金属端子经由连接部分接合。

公开(公告)号：US08922027B2

公开(公告)日：2014-12-30

申请号：US13671970

申请日：2012-11-08

Applicant: Fujitsu Limited

Inventor： Taiji Sakai ,  Nobuhiro Imaizumi

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L23/12 ,  H01L23/00 ,  H01L23/488 ,  G21K5/02 ,  H01L21/67 ,  H01L21/762

CPC classification number: H01L21/76254 ,  B23K20/026 ,  B23K20/24 ,  B23K20/26 ,  B23K2101/42 ,  G21K5/02 ,  H01L21/2686 ,  H01L21/32134 ,  H01L21/67017 ,  H01L21/67069 ,  H01L21/67092 ,  H01L21/67115 ,  H01L21/67144 ,  H01L23/488 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/75 ,  H01L24/81 ,  H01L2224/11462 ,  H01L2224/118 ,  H01L2224/1182 ,  H01L2224/1184 ,  H01L2224/11845 ,  H01L2224/13082 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16501 ,  H01L2224/75102 ,  H01L2224/7525 ,  H01L2224/75251 ,  H01L2224/757 ,  H01L2224/7598 ,  H01L2224/81002 ,  H01L2224/8101 ,  H01L2224/81013 ,  H01L2224/81014 ,  H01L2224/8102 ,  H01L2224/81031 ,  H01L2224/81047 ,  H01L2224/81054 ,  H01L2224/81075 ,  H01L2224/8109 ,  H01L2224/81097 ,  H01L2224/81193 ,  H01L2224/81203 ,  H01L2224/8122 ,  H01L2224/818 ,  H01L2224/8183 ,  H01L2224/81907 ,  H01L2224/81986 ,  H01L2224/83192 ,  H01L2224/9211 ,  H01L2224/97 ,  H01L2924/01029 ,  H01L2924/20105 ,  H01L2924/20108 ,  H01L2924/2021 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2224/81 ,  H01L2224/83

Abstract: According to this disclosure, a method of manufacturing an electronic device is provided, which includes exposing a top surface of a first electrode of a first electronic component to organic acid, irradiating the top surface of the first electrode exposed to the organic acid with ultraviolet light, and bonding the first electrode and a second electrode of a second electronic component by heating and pressing the first electrode and the second electrode each other.

Abstract translation: 根据本发明，提供了一种制造电子器件的方法，其包括将第一电子部件的第一电极的顶表面暴露于有机酸，用紫外线照射暴露于有机酸的第一电极的顶表面 并且通过对所述第一电极和所述第二电极进行加热和加压而将所述第一电极和第二电子部件的第二电极接合。

公开(公告)号：US20140342504A1

公开(公告)日：2014-11-20

申请号：US14452754

申请日：2014-08-06

Applicant: FUJITSU LIMITED

Inventor： Taiji SAKAI ,  Nobuhiro IMAIZUMI

IPC: H01L23/00 ,  G21K5/02 ,  H01L21/3213 ,  H01L21/268 ,  H01L21/67

CPC classification number: H01L21/76254 ,  B23K20/026 ,  B23K20/24 ,  B23K20/26 ,  B23K2101/42 ,  G21K5/02 ,  H01L21/2686 ,  H01L21/32134 ,  H01L21/67017 ,  H01L21/67069 ,  H01L21/67092 ,  H01L21/67115 ,  H01L21/67144 ,  H01L23/488 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/75 ,  H01L24/81 ,  H01L2224/11462 ,  H01L2224/118 ,  H01L2224/1182 ,  H01L2224/1184 ,  H01L2224/11845 ,  H01L2224/13082 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16501 ,  H01L2224/75102 ,  H01L2224/7525 ,  H01L2224/75251 ,  H01L2224/757 ,  H01L2224/7598 ,  H01L2224/81002 ,  H01L2224/8101 ,  H01L2224/81013 ,  H01L2224/81014 ,  H01L2224/8102 ,  H01L2224/81031 ,  H01L2224/81047 ,  H01L2224/81054 ,  H01L2224/81075 ,  H01L2224/8109 ,  H01L2224/81097 ,  H01L2224/81193 ,  H01L2224/81203 ,  H01L2224/8122 ,  H01L2224/818 ,  H01L2224/8183 ,  H01L2224/81907 ,  H01L2224/81986 ,  H01L2224/83192 ,  H01L2224/9211 ,  H01L2224/97 ,  H01L2924/01029 ,  H01L2924/20105 ,  H01L2924/20108 ,  H01L2924/2021 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2224/81 ,  H01L2224/83

Abstract: According to this disclosure, a method of manufacturing an electronic device is provided, which includes exposing a top surface of a first electrode of a first electronic component to organic acid, irradiating the top surface of the first electrode exposed to the organic acid with ultraviolet light, and bonding the first electrode and a second electrode of a second electronic component by heating and pressing the first electrode and the second electrode each other.

Abstract translation: 根据本发明，提供了一种制造电子器件的方法，其包括将第一电子部件的第一电极的顶表面暴露于有机酸，用紫外线照射暴露于有机酸的第一电极的顶表面 并且通过对所述第一电极和所述第二电极进行加热和加压而将所述第一电极和第二电子部件的第二电极接合。

公开(公告)号：US08872336B2

公开(公告)日：2014-10-28

申请号：US13654710

申请日：2012-10-18

Applicant: Chipmos Technologies Inc.

Inventor： Geng-Shin Shen ,  Chung-Pang Chi

IPC: H01L23/48 ,  H01L23/52 ,  H01L23/00

CPC classification number: H01L24/11 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L2224/034 ,  H01L2224/03602 ,  H01L2224/0401 ,  H01L2224/05022 ,  H01L2224/05027 ,  H01L2224/05073 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05172 ,  H01L2224/05184 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/1132 ,  H01L2224/11462 ,  H01L2224/1148 ,  H01L2224/11831 ,  H01L2224/1184 ,  H01L2224/11845 ,  H01L2224/13022 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/1329 ,  H01L2224/133 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2924/00014 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/00012 ,  H01L2224/05552

Abstract: A conductive structure for a semiconductor chip and a method for forming the conductive structure are provided. The semiconductor chip comprises a semiconductor substrate, a pad, a passivation layer and a patterned insulating layer. The patterned insulating layer is disposed on the passivation layer and partially and directly covers the first opening of the pad to expose a second opening. The conductive structure comprises an under bump metal (UBM) layer and a conductive bump. The UBM layer is disposed in the second opening defined by the patterned insulating layer and is electrically connected to the pad. The conductive bump is disposed on the UBM layer and is electrically connected to the UBM layer. The upper surface of the conductive bump is greater than the upper surface of the patterned insulating layer, while the portion of the conductive bump disposed in the second opening is covered by the UBM layer.

Abstract translation: 提供了一种用于半导体芯片的导电结构和用于形成导电结构的方法。 半导体芯片包括半导体衬底，衬垫，钝化层和图案化绝缘层。 图案化的绝缘层设置在钝化层上，并且部分地并且直接覆盖焊盘的第一开口以露出第二开口。 导电结构包括凹凸金属（UBM）层和导电凸块。 UBM层设置在由图案化的绝缘层限定的第二开口中，并且电连接到焊盘。 导电凸块设置在UBM层上并与UBM层电连接。 导电凸块的上表面大于图案化绝缘层的上表面，而布置在第二开口中的导电凸块的部分被UBM层覆盖。

公开(公告)号：US08610269B2

公开(公告)日：2013-12-17

申请号：US13379273

申请日：2010-06-23

Applicant: Kenji Nanba

Inventor： Kenji Nanba

IPC: H01L23/485

CPC classification number: H01L24/11 ,  H01L23/3157 ,  H01L24/13 ,  H01L24/16 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/92 ,  H01L2224/10126 ,  H01L2224/11424 ,  H01L2224/11464 ,  H01L2224/1184 ,  H01L2224/11845 ,  H01L2224/13022 ,  H01L2224/13082 ,  H01L2224/13111 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/16145 ,  H01L2224/27416 ,  H01L2224/27515 ,  H01L2224/2784 ,  H01L2224/27845 ,  H01L2224/29011 ,  H01L2224/29018 ,  H01L2224/29022 ,  H01L2224/29111 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/73104 ,  H01L2224/81193 ,  H01L2224/81201 ,  H01L2224/81801 ,  H01L2224/83193 ,  H01L2224/83201 ,  H01L2224/83855 ,  H01L2224/9211 ,  H01L2224/94 ,  H01L2924/00013 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/0132 ,  H01L2924/014 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2224/11 ,  H01L2224/27 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2924/0105 ,  H01L2224/13099 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/05099 ,  H01L2224/29099 ,  H01L2224/29599 ,  H01L2924/3512 ,  H01L2924/00

Abstract: [Problem] A semiconductor device which achieves a fine pitch, a high throughput and a high connection reliability, especially in flip-chip mounting is provided. A method for manufacturing the semiconductor device and a circuit device using the semiconductor device are also provided.[Means for solving the problem] The semiconductor device has: an electrode; an insulating part having an opening on the electrode; a protruding part formed on the electrode; a protecting part which is formed at the periphery of the protruding part and electrically isolates the protruding part; and a bonding part which is formed on the protecting part by being spaced apart from the protruding part. An upper surface of the protruding part, an upper surface of the protecting part, and an upper surface of the bonding part form the same plane.

Abstract translation: [问题]提供了一种实现细间距，高吞吐量和高连接可靠性的半导体器件，特别是在倒装芯片安装中。 还提供了一种用于制造半导体器件的方法和使用该半导体器件的电路器件。 [解决问题的手段]半导体器件具有：电极; 在所述电极上具有开口的绝缘部; 形成在所述电极上的突出部; 保护部，其形成在突出部的周围，并且使突出部电隔离; 以及通过与所述突出部分间隔开地形成在所述保护部上的接合部。 突出部的上表面，保护部的上表面和接合部的上表面形成同一平面。

公开(公告)号：US20130127047A1

公开(公告)日：2013-05-23

申请号：US13654710

申请日：2012-10-18

Applicant: CHIPMOS TECHNOLOGIES INC.

Inventor： Geng-Shin SHEN ,  Chung-Pang CHI

IPC: H01L23/498 ,  H01L21/768

CPC classification number: H01L24/11 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L2224/034 ,  H01L2224/03602 ,  H01L2224/0401 ,  H01L2224/05022 ,  H01L2224/05027 ,  H01L2224/05073 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05172 ,  H01L2224/05184 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/1132 ,  H01L2224/11462 ,  H01L2224/1148 ,  H01L2224/11831 ,  H01L2224/1184 ,  H01L2224/11845 ,  H01L2224/13022 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/1329 ,  H01L2224/133 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2924/00014 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/00012 ,  H01L2224/05552

Abstract: A conductive structure for a semiconductor chip and a method for forming the conductive structure are provided. The semiconductor chip comprises a semiconductor substrate, a pad, a passivation layer and a patterned insulating layer. The patterned insulating layer is disposed on the passivation layer and partially and directly covers the first opening of the pad to expose a second opening. The conductive structure comprises an under bump metal (UBM) layer and a conductive bump. The UBM layer is disposed in the second opening defined by the patterned insulating layer and is electrically connected to the pad. The conductive bump is disposed on the UBM layer and is electrically connected to the UBM layer. The upper surface of the conductive bump is greater than the upper surface of the patterned insulating layer, while the portion of the conductive bump disposed in the second opening is covered by the UBM layer.

公开(公告)号：US20120168931A1

公开(公告)日：2012-07-05

申请号：US13418454

申请日：2012-03-13

Applicant: Veeraraghavan S. Basker ,  Toshiharu Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  Charles W. Koburger, III ,  Krishna V. Singh

Inventor： Veeraraghavan S. Basker ,  Toshiharu Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  Charles W. Koburger, III ,  Krishna V. Singh

IPC: H01L23/36 ,  H01L21/50 ,  B82Y99/00 ,  B82Y40/00

CPC classification number: H01L23/373 ,  B82Y10/00 ,  B82Y40/00 ,  H01L21/6835 ,  H01L23/3157 ,  H01L23/433 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/27 ,  H01L24/81 ,  H01L24/94 ,  H01L29/0657 ,  H01L2221/6835 ,  H01L2221/68377 ,  H01L2224/0401 ,  H01L2224/05026 ,  H01L2224/05186 ,  H01L2224/05561 ,  H01L2224/05564 ,  H01L2224/05571 ,  H01L2224/05655 ,  H01L2224/05657 ,  H01L2224/0566 ,  H01L2224/10135 ,  H01L2224/113 ,  H01L2224/11845 ,  H01L2224/13021 ,  H01L2224/13076 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/13184 ,  H01L2224/13187 ,  H01L2224/13193 ,  H01L2224/16221 ,  H01L2224/1703 ,  H01L2224/17515 ,  H01L2224/274 ,  H01L2224/73253 ,  H01L2224/81139 ,  H01L2224/81191 ,  H01L2224/81193 ,  H01L2224/81493 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/04941 ,  H01L2924/14 ,  H01L2924/04953 ,  H01L2224/05552

Abstract: Disclosed are embodiments of an improved semiconductor wafer structure having protected clusters of carbon nanotubes (CNTs) on the back surface and a method of forming the improved semiconductor wafer structure. Also disclosed are embodiments of a semiconductor module with exposed CNTs on the back surface for providing enhanced thermal dissipation in conjunction with a heat sink and a method of forming the semiconductor module using the disclosed semiconductor wafer structure.

Abstract translation: 公开了在后表面上具有碳纳米管（CNT）的保护簇的改进的半导体晶片结构的实施方案和形成改进的半导体晶片结构的方法。 还公开了在后表面上具有暴露的CNT的半导体模块的实施例，用于与散热器一起提供增强的散热以及使用所公开的半导体晶片结构形成半导体模块的方法。

公开(公告)号：US20120032296A1

公开(公告)日：2012-02-09

申请号：US13091204

申请日：2011-04-21

Applicant: Naoki Kosaka ,  Hirotaka Amasuga ,  Kou Kanaya

Inventor： Naoki Kosaka ,  Hirotaka Amasuga ,  Kou Kanaya

IPC: H01L23/48 ,  H01L21/50

CPC classification number: H01L24/80 ,  H01L21/6835 ,  H01L23/49833 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/81 ,  H01L24/83 ,  H01L24/94 ,  H01L25/0657 ,  H01L25/50 ,  H01L29/2003 ,  H01L29/7322 ,  H01L2221/6835 ,  H01L2221/68381 ,  H01L2224/1146 ,  H01L2224/11831 ,  H01L2224/11845 ,  H01L2224/13144 ,  H01L2224/16225 ,  H01L2224/274 ,  H01L2224/27831 ,  H01L2224/27845 ,  H01L2224/29011 ,  H01L2224/291 ,  H01L2224/29101 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/8001 ,  H01L2224/80013 ,  H01L2224/80123 ,  H01L2224/80129 ,  H01L2224/8013 ,  H01L2224/80132 ,  H01L2224/80201 ,  H01L2224/80203 ,  H01L2224/80895 ,  H01L2224/81191 ,  H01L2224/83191 ,  H01L2225/06513 ,  H01L2225/06551 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01068 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/014 ,  H01L2924/10329 ,  H01L2924/1305 ,  H01L2924/14 ,  H01L2924/1423 ,  H05K1/14 ,  H05K2201/047 ,  H05K2201/10515 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01049 ,  H01L2924/01031

Abstract: A semiconductor circuit substrate includes a transistor-forming substrate and a circuit-forming substrate. The transistor-forming substrate is a GaN substrate and has a Bipolar Junction Transistor (BJT) located in its top surface. The bottom surface of the transistor-forming substrate is flat and has contact regions. The circuit-forming substrate is a material other than a compound semiconductor and has no semiconductor active elements. The circuit-forming substrate has a flat top surface, contact regions buried in and exposed at the top surface, and passive circuits. The transistor-forming substrate and the circuit-forming substrate are directly bonded together without any intervening film, such as an insulating film.

Abstract translation: 半导体电路基板包括晶体管形成基板和电路形成基板。 晶体管形成衬底是GaN衬底并且具有位于其顶表面中的双极结晶体管（BJT）。 晶体管形成基板的底表面是平坦的并且具有接触区域。 电路形成用基板是化合物半导体以外的材料，不具有半导体活性元素。 电路形成基板具有平坦的顶表面，埋入并暴露在顶表面的接触区域和无源电路。 晶体管形成基板和电路形成基板直接接合在一起，而没有任何中间膜，例如绝缘膜。

公开(公告)号：US11973046B2

公开(公告)日：2024-04-30

申请号：US17465449

申请日：2021-09-02

Applicant: SJ Semiconductor(Jiangyin) Corporation

Inventor： Jiashan Yin ,  Zuyuan Zhou ,  Xingtao Xue ,  Chengchung Lin

IPC: H01L21/3065 ,  H01L23/00

CPC classification number: H01L24/13 ,  H01L21/3065 ,  H01L24/11 ,  H01L2224/11831 ,  H01L2224/11845 ,  H01L2224/13022 ,  H01L2224/13147 ,  H01L2224/1357 ,  H01L2224/136

Abstract: The present disclosure provides a semiconductor structure and a method for preparing it. After planarization of the Cu layer, by means of wet etch process, Cu residues near an edge of a Cu post can be effectively removed, and a first height difference is configured to be between the Cu post and an insulating layer. Further, an Si substrate is then dry etched, so that a second height difference is configured to be between the Si substrate and the insulating layer, and the second height difference is arranged to be greater than the first height difference. In this way, a connection of Cu inside and outside the insulating layer may be further avoided, thereby effectively avoiding an influence on electrical properties of a device.