公开(公告)号：US09711212B2

公开(公告)日：2017-07-18

申请号：US15090216

申请日：2016-04-04

Applicant: Unity Semiconductor Corporation

Inventor： Christophe Chevallier ,  Chang Hua Siau

IPC: G11C11/00 ,  G11C13/00 ,  G11C8/08 ,  G11C8/10 ,  H03K3/356 ,  H03K19/0185

CPC classification number: G11C13/0023 ,  G11C8/08 ,  G11C8/10 ,  G11C13/0007 ,  G11C13/0028 ,  G11C2213/31 ,  G11C2213/71 ,  G11C2213/77 ,  H03K3/356104 ,  H03K19/018521

Abstract: A system includes a cross-point memory array and a decoder circuit coupled to the cross-point memory array. The decoder circuit includes a predecoder having predecode logic to generate a control signal and a level shifter circuit to generate a voltage signal. The decoder circuit further includes a post-decoder coupled to the predecoder, the post-decoder including a first stage and a second stage coupled to the first stage, the control signal to control the first stage and the second stage to route the voltage signal through the first stage and the second stage to a selected conductive array line of a plurality of conductive array lines coupled to a memory array.

公开(公告)号：US09306549B2

公开(公告)日：2016-04-05

申请号：US14688060

申请日：2015-04-16

Applicant: Unity Semiconductor Corporation

Inventor： Christophe Chevallier ,  Chang Hua Siau

IPC: G11C11/34 ,  H03K3/356 ,  G11C13/00 ,  G11C8/08 ,  G11C8/10

CPC classification number: G11C13/0023 ,  G11C8/08 ,  G11C8/10 ,  G11C13/0007 ,  G11C13/0028 ,  G11C2213/31 ,  G11C2213/71 ,  G11C2213/77 ,  H03K3/356104 ,  H03K19/018521

Abstract: Circuitry for generating voltage levels operative to perform data operations on non-volatile re-writeable memory arrays are disclosed. In some embodiments an integrated circuit includes a substrate and a base layer formed on the substrate to include active devices configured to operate within a first voltage range. Further, the integrated circuit can include a cross-point memory array formed above the base layer and including re-writable two-terminal memory cells that are configured to operate, for example, within a second voltage range that is greater than the first voltage range. Conductive array lines in the cross-point memory array are electrically coupled with the active devices in the base layer. The integrated circuit also can include X-line decoders and Y-line decoders that include devices that operate in the first voltage range. The active devices can include other active circuitry such as sense amps for reading data from the memory cells, for example.

公开(公告)号：US09245599B1

公开(公告)日：2016-01-26

申请号：US14887547

申请日：2015-10-20

Applicant: SANDISK 3D LLC

Inventor： Anurag Nigam ,  Gopinath Balakrishnan

IPC: G11C13/00 ,  G11C7/08 ,  G11C16/26 ,  G11C16/04

CPC classification number: G11C7/08 ,  G11C11/5614 ,  G11C11/5678 ,  G11C11/5685 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0011 ,  G11C13/004 ,  G11C13/0069 ,  G11C16/0483 ,  G11C16/26 ,  G11C2211/563 ,  G11C2213/31 ,  G11C2213/32 ,  G11C2213/71 ,  G11C2213/75

Abstract: Methods for determining memory cell states during a read operation using a detection scheme that reduces the area of detection circuitry for detecting the states of the memory cells by time multiplexing the use of portions of the detection circuitry are described. The read operation may include a precharge phase, a sensing phase, and a detection phase. In some embodiments, a first bit line and a second bit line may be precharged to a read voltage in parallel, and then sensing and/or detection of selected memory cells corresponding with the first bit line and the second bit line may be performed serially using the same detection circuitry by time multiplexing the use of the detection circuitry. In some cases, the time multiplexed detection circuitry may be used for detecting two or more states corresponding with two or more memory cells being sensed during a read operation.

公开(公告)号：US20150318471A1

公开(公告)日：2015-11-05

申请号：US14647793

申请日：2013-11-06

Applicant: SONY CORPORATION

Inventor： Kazuhiro OHBA ,  Hiroaki SEI

IPC: H01L45/00 ,  G11C13/00

CPC classification number: H01L45/085 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0009 ,  G11C13/004 ,  G11C13/0069 ,  G11C2213/31 ,  G11C2213/35 ,  G11C2213/56 ,  H01L27/2436 ,  H01L27/2463 ,  H01L27/2472 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/142 ,  H01L45/143 ,  H01L45/144 ,  H01L45/145 ,  H01L45/147

Abstract: There are provided a storage device and a storage unit capable of improving retention performance of an intermediate resistance value in writing at a low current, and a storage device and a storage unit capable of reducing random telegraph noise. A storage device of one embodiment of the present technology includes a first electrode, a storage layer, and a second electrode in this order, and the storage layer includes: an ion source layer including one or more kinds of chalcogen elements selected from tellurium (Te), sulfur (S), and selenium (Se), and one or more kinds of transition metal elements selected from Group 4 elements, Group 5 elements, and Group 6 elements of the periodic table; and a resistance change layer including boron (B) and oxygen (O). A storage device of another embodiment of the present technology includes the above-described ion source layer and a resistance change layer including one or more kinds of transaction metal elements selected from Group 4 elements, Group 5 elements, and Group 6 elements of the periodic table, and oxygen (O).

Abstract translation: 提供了能够以低电流改善中间电阻值的保持性能的存储装置和存储单元，以及能够减少随机电报噪声的存储装置和存储单元。 本技术的一个实施例的存储装置依次包括第一电极，存储层和第二电极，并且存储层包括：离子源层，包括选自碲（Te）中的一种或多种硫属元素 ），硫（S）和硒（Se）以及选自元素周期表第4族元素，第5族元素和第6族元素的一种或多种过渡金属元素; 和包含硼（B）和氧（O）的电阻变化层。 本技术的另一实施例的存储装置包括上述离子源层和包括选自元素周期表的第4族元素，第5族元素和第6族元素中的一种或多种交易金属元素的电阻变化层 ，和氧（O）。

公开(公告)号：US09159408B2

公开(公告)日：2015-10-13

申请号：US14167694

申请日：2014-01-29

Applicant: Unity Semiconductor Corporation

Inventor： Christophe J. Chevallier ,  Steve Kuo-Ren Hsia ,  Wayne Kinney ,  Steven Longcor ,  Darrell Rinerson ,  John Sanchez ,  Philip F. S. Swab ,  Edmond R. Ward

IPC: H01L45/00 ,  G11C13/00 ,  G11C11/16 ,  G11C11/56 ,  H01L27/24

CPC classification number: H01L27/2463 ,  G11C11/16 ,  G11C11/5685 ,  G11C13/0002 ,  G11C13/0007 ,  G11C13/004 ,  G11C13/0069 ,  G11C13/0097 ,  G11C2013/009 ,  G11C2213/15 ,  G11C2213/31 ,  G11C2213/32 ,  G11C2213/71 ,  G11C2213/77 ,  G11C2213/79 ,  H01L27/24 ,  H01L27/2481 ,  H01L45/04 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/146 ,  H01L45/147 ,  H01L45/1633 ,  H01L45/1658

Abstract: A memory cell including conductive oxide electrodes is disclosed. The memory cell includes a memory element operative to store data as a plurality of resistive states. The memory element includes a layer of a conductive metal oxide (CMO) (e.g., a perovskite) in contact with an electrode that may comprise one or more layers of material. At least one of those layers of material can be a conductive oxide (e.g., a perovskite such as LaSrCoO3-LSCoO or LaNiO3-LNO) that is in contact with the CMO. The conductive oxide layer can be selected as a seed layer operative to provide a good lattice match with and/or a lower crystallization temperature for the CMO. The conductive oxide layer may also be in contact with a metal layer (e.g., Pt). The memory cell additionally exhibits non-linear IV characteristics, which can be favorable in certain arrays, such as non-volatile two-terminal cross-point memory arrays.

Abstract translation: 公开了一种包括导电氧化物电极的存储单元。 存储单元包括用于将数据存储为多个电阻状态的存储元件。 存储元件包括与可包括一层或多层材料的电极接触的导电金属氧化物（CMO）（例如，钙钛矿）层。 这些材料层中的至少一层可以是与CMO接触的导电氧化物（例如，诸如LaSrCoO3-LSCoO或LaNiO3-LNO的钙钛矿）。 可以选择导电氧化物层作为晶种层，以为CMO提供良好的晶格匹配和/或较低的结晶温度。 导电氧化物层也可以与金属层（例如Pt）接触。 存储单元还具有非线性IV特性，这在某些阵列中是有利的，例如非易失性两端交叉点存储阵列。

公开(公告)号：US20150129935A1

公开(公告)日：2015-05-14

申请号：US14602559

申请日：2015-01-22

Applicant: Micron Technology, Inc.

Inventor： Sanh D. Tang ,  Roger W. Lindsay ,  Krishna K. Parat

IPC: H01L23/52 ,  H01L27/10

CPC classification number: H01L27/11582 ,  G11C13/0007 ,  G11C2213/11 ,  G11C2213/31 ,  G11C2213/32 ,  G11C2213/71 ,  G11C2213/75 ,  H01L23/52 ,  H01L23/528 ,  H01L27/10 ,  H01L27/101 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/249 ,  H01L45/141 ,  H01L45/142 ,  H01L45/143 ,  H01L45/144 ,  H01L45/145 ,  H01L45/146 ,  H01L45/147 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of forming circuitry components includes forming a stack of horizontally extending and vertically overlapping features. The stack has a primary portion and an end portion. At least some of the features extend farther in the horizontal direction in the end portion moving deeper into the stack in the end portion. Operative structures are formed vertically through the features in the primary portion and dummy structures are formed vertically through the features in the end portion. Horizontally elongated openings are formed through the features to form horizontally elongated and vertically overlapping lines from material of the features. The lines individually extend from the primary portion into the end portion, and individually laterally about sides of vertically extending portions of both the operative structures and the dummy structures. Sacrificial material that is elevationally between the lines is at least partially removed in the primary and end portions laterally between the horizontally elongated openings. Other aspects and implementations are disclosed.

Abstract translation: 形成电路部件的方法包括形成水平延伸和垂直重叠特征的堆叠。 堆叠具有主要部分和端部。 至少一些特征在末端部分中更深地移动到堆叠中的端部中在水平方向上延伸得更远。 操作结构通过主要部分的特征垂直地形成，并且虚拟结构通过端部中的特征垂直地形成。 通过特征形成水平细长的开口以从特征的材料形成水平细长的和垂直重叠的线。 这些线分别从主要部分延伸到端部，并且单独地横向地围绕操作结构和虚拟结构的垂直延伸部分的侧面。 至少部分地，在水平伸长的开口之间的主要端部和端部中部分地去除在线之间高度的牺牲材料。 公开了其他方面和实现。

公开(公告)号：US09001551B2

公开(公告)日：2015-04-07

申请号：US13488869

申请日：2012-06-05

Applicant: Man Chang ,  Young-bae Kim ,  Dong-soo Lee ,  Chang-bum Lee ,  Seung-ryul Lee ,  Chang-jung Kim ,  Myoung-jae Lee ,  Kyung-min Kim

Inventor： Man Chang ,  Young-bae Kim ,  Dong-soo Lee ,  Chang-bum Lee ,  Seung-ryul Lee ,  Chang-jung Kim ,  Myoung-jae Lee ,  Kyung-min Kim

IPC: G11C11/00 ,  G11C13/00 ,  G11C11/56

CPC classification number: G11C13/0069 ,  G11C11/5685 ,  G11C13/0007 ,  G11C13/0033 ,  G11C2013/0076 ,  G11C2013/009 ,  G11C2013/0092 ,  G11C2211/5625 ,  G11C2213/31 ,  G11C2213/32

Abstract: In a method of operating a semiconductor device, a resistance value of a variable resistance element is changed from a first resistance value to a second resistance value by applying a first voltage to the variable resistance element; and a first current that flows through the variable resistance element is sensed. A second voltage for changing the resistance value of the variable resistance element from the second resistance value to the first resistance value is modulated based on a dispersion of the first current, and the first voltage is re-applied to the variable resistance element based on a dispersion of the first current.

Abstract translation: 在操作半导体器件的方法中，通过向可变电阻元件施加第一电压，可变电阻元件的电阻值从第一电阻值改变为第二电阻值; 并且感测流过可变电阻元件的第一电流。 基于第一电流的偏差来调制用于将可变电阻元件的电阻值从第二电阻值改变为第一电阻值的第二电压，并且基于第一电压将第一电压重新施加到可变电阻元件 第一电流的分散。

公开(公告)号：US08964447B2

公开(公告)日：2015-02-24

申请号：US13058952

申请日：2009-06-24

Applicant: Hiroyuki Nagashima ,  Hirofumi Inoue

Inventor： Hiroyuki Nagashima ,  Hirofumi Inoue

IPC: G11C11/00 ,  G11C13/00

CPC classification number: G11C13/003 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0011 ,  G11C13/0023 ,  G11C13/004 ,  G11C13/0069 ,  G11C2213/31 ,  G11C2213/72

Abstract: A nonvolatile semiconductor memory device comprises a cell array including a plurality of first lines, a plurality of second lines intersecting the plurality of first lines, and a plurality of memory cells arranged in matrix and connected at intersections of the first and second lines between both lines, each memory cell containing a serial circuit of an electrically erasable programmable variable resistive element of which resistance is nonvolatilely stored as data and a non-ohmic element; and a plurality of access circuits operative to simultaneously access the memory cells physically separated from each other in the cell array.

Abstract translation: 一种非易失性半导体存储器件，包括一个单元阵列，该单元阵列包括多个第一线，与该多条第一线相交的多个第二线，以及多个存储单元，被布置成矩阵并连接在两条线之间的第一和第二线的交点处 每个存储单元包含其中电阻被非易失性地存储为数据的电可擦除可编程可变电阻元件和非欧姆元件的串行电路; 以及多个访问电路，其操作以同时访问在单元阵列中彼此物理分离的存储单元。

公开(公告)号：US08817533B2

公开(公告)日：2014-08-26

申请号：US13487427

申请日：2012-06-04

Applicant: Kailash Gopalakrishnan

Inventor： Kailash Gopalakrishnan

IPC: G11C11/00

CPC classification number: H01L27/2409 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1675 ,  G11C13/0007 ,  G11C13/0011 ,  G11C13/003 ,  G11C13/0069 ,  G11C2013/0073 ,  G11C2213/31 ,  G11C2213/32 ,  G11C2213/51 ,  G11C2213/71 ,  G11C2213/72 ,  G11C2213/76 ,  H01L27/224

Abstract: A crosspoint array has been shown having a plurality of bitlines and wordlines; and a plurality of crossbar elements, with each crossbar element being disposed between a bitline and a wordline and with each crossbar element having at least a solid electrolyte material used as a rectifier in series with a symmetric or substantially symmetric resistive memory node. The crossbar elements are responsive to the following voltages: a first set of voltages to transition the solid electrolyte in the crossbar elements from an OFF state to an ON state, a second set of voltages to read or program the symmetric resistive memory, and a third set of voltages to transition solid electrolyte from an ON state to an OFF state.

Abstract translation: 已经示出了具有多个位线和字线的交叉点阵列; 以及多个横杆元件，其中每个横杆元件设置在位线和字线之间，并且每个横杆元件至少具有用作与对称或基本上对称的电阻性存储器节点串联的整流器的固体电解质材料。 交叉开关元件响应于以下电压：将交叉开关元件中的固体电解质从OFF状态转变到导通状态的第一组电压，用于读取或编程对称电阻性存储器的第二组电压，以及第三组 一组电压将固体电解质从ON状态转变为OFF状态。

公开(公告)号：US08809114B2

公开(公告)日：2014-08-19

申请号：US13964157

申请日：2013-08-12

Applicant: SanDisk 3D LLC

Inventor： April D. Schricker ,  S. Brad Herner ,  Mark H. Clark

IPC: H01L29/02

CPC classification number: H01L45/1641 ,  G11C13/0007 ,  G11C2213/31 ,  G11C2213/33 ,  G11C2213/56 ,  G11C2213/71 ,  G11C2213/72 ,  G11C2213/79 ,  H01L27/2409 ,  H01L27/2436 ,  H01L27/2481 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/145 ,  H01L45/146 ,  H01L45/1633 ,  H01L45/1675

Abstract: A method of forming a memory cell is provided that includes forming a steering element above a substrate, forming a material layer on the substrate, patterning and etching the material layer, and oxidizing the patterned and etched material layer to form a reversible resistance-switching material. Numerous other aspects are provided.

Abstract translation: 提供一种形成存储单元的方法，其包括在基板上形成操纵元件，在基板上形成材料层，图案化和蚀刻材料层，以及氧化图案化和蚀刻的材料层以形成可逆电阻切换材料 。 提供了许多其他方面。