Decoding scheme for bipolar-based diode three-dimensional memory requiring unipolar programming
    2.
    发明授权
    Decoding scheme for bipolar-based diode three-dimensional memory requiring unipolar programming 有权
    需要单极编程的双极型二极管三维存储器的解码方案

    公开(公告)号:US08842491B2

    公开(公告)日:2014-09-23

    申请号:US13551597

    申请日:2012-07-17

    Abstract: A system and method for operating a unipolar memory cell array including a bidirectional access diode. The system includes a column voltage switch electrically coupled to a plurality of column voltages. The column voltage switch includes an output electrically coupled to the bidirectional access diode. The plurality of column voltages includes at least one select column voltage and one deselect column voltage. The system includes a row voltage switch electrically coupled to a plurality of row voltages. The row voltage switch includes an output electrically coupled to the bidirectional access diode. The plurality of row voltages includes at least one select row voltage and one deselect row voltage. The system includes a column and row decoder electrically coupled to a select line of the column and row voltage switches, respectively.

    Abstract translation: 一种用于操作包括双向存取二极管的单极存储单元阵列的系统和方法。 该系统包括电耦合到多个列电压的列电压开关。 列电压开关包括电耦合到双向存取二极管的输出。 多个列电压包括至少一个选择列电压和一个取消选择列电压。 该系统包括电耦合到多个行电压的行电压开关。 行电压开关包括电耦合到双向存取二极管的输出。 多个行电压包括至少一个选择行电压和一个取消选择行电压。 该系统包括分别电耦合到列的选择线和行电压开关的列和行解码器。

    Non-volatile memory crosspoint repair
    3.
    发明授权
    Non-volatile memory crosspoint repair 有权
    非易失性存储器交叉点修复

    公开(公告)号:US08811060B2

    公开(公告)日:2014-08-19

    申请号:US13485748

    申请日:2012-05-31

    Abstract: A device for use with a memory cross-point array of elements, each of which comprises a selection device in series with a state-holding device, in one embodiment includes a controller, configured to apply at least one voltage and/or current pulse to a selected one or more of the elements, said selected one or more of the elements including a partially- or completely-shorted selection device, so that said partially- or completely-shorted selection device passes enough current so as to damage its corresponding state-holding device and place said corresponding state-holding device in a highly resistive state, while any other selection device that is not partially- or completely-shorted passes less current so that the state-holding device corresponding to said other selection device remains unaffected. Additional systems and methods are also presented.

    Abstract translation: 一种与存储器交叉点阵列元件一起使用的装置,每个元件包括与状态保持装置串联的选择装置,在一个实施例中包括控制器,被配置为将至少一个电压和/或电流脉冲施加到 所选择的一个或多个元件,所述选定的一个或多个元件包括部分或完全短路的选择装置,使得所述部分或完全短路的选择装置通过足够的电流,以便损坏其对应的状态 - 并且将所述对应的状态保持装置置于高电阻状态,而没有部分或全部短路的任何其他选择装置通过较少电流,使得与所述其他选择装置对应的状态保持装置保持不受影响。 还介绍了其他系统和方法。

    Decoding scheme for bipolar-based diode three-dimensional memory requiring bipolar programming
    4.
    发明授权
    Decoding scheme for bipolar-based diode three-dimensional memory requiring bipolar programming 失效
    需要双极性编程的双极型二极管三维存储器的解码方案

    公开(公告)号:US08755213B2

    公开(公告)日:2014-06-17

    申请号:US13407848

    申请日:2012-02-29

    Abstract: A system and method for operating a bipolar memory cell array including a bidirectional access diode. The system includes a column voltage. The column voltage switch includes column voltages and an output electrically coupled to the bidirectional access diode. The column voltages include at least one write-one column voltage and at least one write-zero column voltage. The system also includes a row voltage switch. The row voltage switch includes row voltages and an output electrically coupled to the bidirectional access diode. The row voltages include at least one write-one row voltage and at least one write-zero row voltage. The system further includes a column decoder and a row decoder electrically coupled to a select line of the column voltage switch and row voltage switch, respectively. The system includes a write driver electrically coupled to the select lines of the row and column switches.

    Abstract translation: 一种用于操作包括双向存取二极管的双极存储单元阵列的系统和方法。 该系统包括列电压。 列电压开关包括列电压和电耦合到双向存取二极管的输出。 列电压包括至少一个写一列电压和至少一个写零列电压。 该系统还包括行电压开关。 行电压开关包括行电压和电耦合到双向存取二极管的输出。 行电压包括至少一个写入一行电压和至少一个写入零行电压。 该系统还包括分别与列电压开关和行电压开关的选择线电耦合的列解码器和行解码器。 该系统包括电耦合到行和列开关的选择线的写入驱动器。

    ELECTRONICALLY SCANNABLE MULTIPLEXING DEVICE
    6.
    发明申请
    ELECTRONICALLY SCANNABLE MULTIPLEXING DEVICE 有权
    电子扫描多路复用器件

    公开(公告)号:US20100284214A1

    公开(公告)日:2010-11-11

    申请号:US12839451

    申请日:2010-07-20

    Abstract: An electronically scannable multiplexing device is capable of addressing multiple bits within a volatile or non-volatile memory cell. The multiplexing device generates an electronically scannable conducting channel with two oppositely formed depletion regions. The depletion width of each depletion region is controlled by a voltage applied to a respective control gate at each end of the multiplexing device. The present multi-bit addressing technique allows, for example, 10 to 100 bits of data to be accessed or addressed at a single node. The present invention can also be used to build a programmable nanoscale logic array or for randomly accessing a nanoscale sensor array.

    Abstract translation: 电子扫描复用设备能够寻址易失性或非易失性存储器单元内的多个位。 多路复用装置产生具有两个相对形成的耗尽区的电子扫描导电通道。 每个耗尽区的耗尽宽度由施加到多路复用器件每端的相应控制栅极的电压控制。 目前的多位寻址技术允许例如在单个节点上访问或寻址10到100位的数据。 本发明还可用于构建可编程纳米尺度逻辑阵列或用于随机访问纳米级传感器阵列。

    Electronically scannable multiplexing device
    7.
    发明授权
    Electronically scannable multiplexing device 失效
    电子可扫描多路复用器件

    公开(公告)号:US07795044B2

    公开(公告)日:2010-09-14

    申请号:US12338275

    申请日:2008-12-18

    Abstract: An electronically scannable multiplexing device is capable of addressing multiple bits within a volatile or non-volatile memory cell. The multiplexing device generates an electronically scannable conducting channel with two oppositely formed depletion regions. The depletion width of each depletion region is controlled by a voltage applied to a respective control gate at each end of the multiplexing device. The present multi-bit addressing technique allows, for example, 10 to 100 bits of data to be accessed or addressed at a single node. The present invention can also be used to build a programmable nanoscale logic array or for randomly accessing a nanoscale sensor array.

    Abstract translation: 电子扫描复用设备能够寻址易失性或非易失性存储器单元内的多个位。 多路复用装置产生具有两个相对形成的耗尽区的电子扫描导电通道。 每个耗尽区的耗尽宽度由施加到多路复用器件每端的相应控制栅极的电压控制。 目前的多位寻址技术允许例如在单个节点上访问或寻址10到100位的数据。 本发明还可用于构建可编程纳米尺度逻辑阵列或用于随机访问纳米级传感器阵列。

    Rectifying element for a crosspoint based memory array architecture
    8.
    发明授权
    Rectifying element for a crosspoint based memory array architecture 有权
    用于基于交叉点的存储器阵列架构的整流元件

    公开(公告)号:US07382647B1

    公开(公告)日:2008-06-03

    申请号:US11679785

    申请日:2007-02-27

    Abstract: An asymmetrically programmed memory material (such as a solid electrolyte material) is described for use as a rectifying element for driving symmetric or substantially symmetric resistive memory elements in a crosspoint memory architecture. A solid electrolyte element (SE) has very high resistance in the OFF state and very low resistance in the ON state (because it is a metallic filament in the ON state). These attributes make it a near ideal diode. During the passage of current (during program/read/erase) of the memory element, the solid electrolyte material also programs into the low resistance state. The final state of the solid electrolyte material is reverted to a high resistance state while making sure that the final state of the memory material is the one desired.

    Abstract translation: 描述了一种不对称编程的记忆材料(例如固体电解质材料),用作整流元件,用于驱动交叉点存储器架构中的对称或基本对称的电阻性存储器元件。 固体电解质元件(SE)在OFF状态下具有非常高的电阻,并且在ON状态下具有非常低的电阻(因为它是处于ON状态的金属灯丝)。 这些属性使其成为接近理想的二极管。 在存储元件的电流(在编程/读取/擦除期间)期间,固体电解质材料也编程到低电阻状态。 固体电解质材料的最终状态被还原成高电阻状态,同时确保记忆材料的最终状态是期望的。

    3D architecture for bipolar memory using bipolar access device
    10.
    发明授权
    3D architecture for bipolar memory using bipolar access device 有权
    使用双极存取器件的双极存储器的3D架构

    公开(公告)号:US08873271B2

    公开(公告)日:2014-10-28

    申请号:US13209405

    申请日:2011-08-14

    Abstract: Memory device and method for fabricating a memory device on two layers of a semiconductor wafer. An example device includes bit lines and word lines fabricated at one layer of a semiconductor wafer and re-writable nonvolatile memory cells that include a two-terminal access device with a bidirectional voltage-current characteristics for positive and negative voltages applied at the terminals. Additionally, a drive circuit electrically coupled to the memory cells and configured to program the memory cells is fabricated at another layer of the semiconductor wafer. Another example embodiment includes a memory device where a plurality of memory arrays are fabricated at one layer of a semiconductor wafer and a plurality of drive circuits electrically coupled to the memory cells and configured to read the memory cells are fabricated at a second layer of the semiconductor wafer.

    Abstract translation: 用于在两层半导体晶片上制造存储器件的存储器件和方法。 示例性器件包括在半导体晶片的一个层处制造的位线和字线以及包括具有用于在端子处施加的正电压和负电压的双向电压 - 电流特性的双端子存取器件的可重写非易失性存储器单元。 此外,在半导体晶片的另一层处制造电耦合到存储器单元并被配置为对存储器单元进行编程的驱动电路。 另一示例性实施例包括存储器件,其中在半导体晶片的一个层处制造多个存储器阵列,并且电耦合到存储器单元并被配置为读取存储器单元的多个驱动电路在半导体的第二层处制造 晶圆。

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