公开(公告)号：US20240365556A1

公开(公告)日：2024-10-31

申请号：US18769532

申请日：2024-07-11

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chieh Lee ,  Chia-En Huang ,  Yi-Ching Liu ,  Wen-Chang Cheng ,  Yih Wang

IPC: H10B51/20 ,  G11C5/04 ,  G11C5/06 ,  G11C11/22 ,  H10B51/10 ,  H10B51/30 ,  H10B51/40

CPC classification number: H10B51/20 ,  G11C5/04 ,  G11C5/063 ,  G11C11/223 ,  G11C11/2273 ,  H10B51/10 ,  H10B51/30 ,  H10B51/40 ,  G11C11/2255 ,  G11C11/2257

Abstract: In some embodiments, an integrated circuit (IC) device includes an active semiconductor layer, a circuitry formed within the active semiconductor layer, a region including conductive layers formed in a back-end-of-line (BEOL) layer above the active semiconductor layer, and a memory module formed in the BEOL layer. The memory device includes a three-dimensional array of memory cells, each adapted to store a weight value, and adapted to generate at each memory cell a signal indicative of a product between the stored weight value and an input signal applied to the memory cell. The memory module is further adapted to transmit the product signals from the memory cell simultaneously in the direction of the active semiconductor layer.

公开(公告)号：US12014768B2

公开(公告)日：2024-06-18

申请号：US17589729

申请日：2022-01-31

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Chieh Lee ,  Chia-En Huang ,  Yi-Ching Liu ,  Wen-Chang Cheng ,  Yih Wang

IPC: G11C11/4091 ,  G11C5/06 ,  G11C11/4094 ,  G11C11/4096 ,  H03K19/20

CPC classification number: G11C11/4091 ,  G11C5/063 ,  G11C11/4094 ,  G11C11/4096 ,  H03K19/20

Abstract: A memory circuit includes first and second circuits. The first circuit includes a DRAM array including a plurality of bit lines, and the second circuit includes a computation circuit including a sense amplifier circuit. A boundary layer is positioned between the first and second circuits, and the boundary layer includes a plurality of via structures configured to electrically connect the plurality of bit lines to the sense amplifier circuit.

公开(公告)号：US11984165B2

公开(公告)日：2024-05-14

申请号：US17752662

申请日：2022-05-24

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chun-Ying Lee ,  Chia-En Huang ,  Chieh Lee

IPC: G11C16/08 ,  G11C16/04 ,  H10B41/20 ,  H10B43/20

CPC classification number: G11C16/08 ,  G11C16/0483 ,  H10B41/20 ,  H10B43/20

Abstract: A memory device includes a plurality of word lines (WLs). The memory device includes a plurality of drivers that are each configured to control a corresponding one of the plurality of WLs and each comprise a first transistor having a first conductive type and a second transistor having a second conductive type. The first transistor of a first one of the drivers is formed in a first well of a substrate, and the second transistor of the first driver is formed in a second well of the substrate. The first well is spaced apart from the second well.

公开(公告)号：US11943936B2

公开(公告)日：2024-03-26

申请号：US17400615

申请日：2021-08-12

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Yu-Der Chih ,  May-Be Chen ,  Yun-Sheng Chen ,  Jonathan Tsung-Yung Chang ,  Wen Zhang Lin ,  Chrong Jung Lin ,  Ya-Chin King ,  Chieh Lee ,  Wang-Yi Lee

IPC: H10B63/00 ,  H01L29/40 ,  H01L29/78

CPC classification number: H10B63/30 ,  H01L29/401 ,  H01L29/785

Abstract: A semiconductor device and a method of manufacturing the same are provided. The semiconductor device includes a first transistor, a first resistive random access memory (RRAM) resistor, and a second RRAM resistor. The first resistor includes a first resistive material layer, a first electrode shared by the second resistor, and a second electrode. The second resistor includes the first electrode, a second resistive material layer, and a third electrode. The first electrode is electrically coupled to the first transistor.

公开(公告)号：US20230385625A1

公开(公告)日：2023-11-30

申请号：US17824306

申请日：2022-05-25

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chieh Lee ,  Chia-En Huang ,  Yi-Chang Liu ,  Wen-Chang Cheng ,  Yih Wang

IPC: G06N3/063 ,  G06F7/544 ,  H03M1/12

CPC classification number: G06N3/0635 ,  G06F7/5443 ,  H03M1/12

Abstract: Disclosed herein are related to a device for performing neuromorphic computing. In one aspect, a device includes a back end of line layer including a three-dimensional memory array. The three-dimensional memory array may include a plurality of memory cells to store a plurality sets of weight values of a neural network model. In one aspect, the device includes a front end of line layer including a controller. The controller may apply one or more input voltages corresponding to an input to the neural network model to the three-dimensional memory array, and receive one or more output voltages from the three-dimensional memory array to perform computations of the neural network model.

公开(公告)号：US20220358993A1

公开(公告)日：2022-11-10

申请号：US17643191

申请日：2021-12-08

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chieh Lee ,  Yi-Ching Liu ,  Chia-En Huang ,  Wen-Chang Cheng ,  Jonathan Tsung-Yung Chang

IPC: G11C11/4091 ,  H01L27/108

Abstract: A memory structure includes a first memory array having bit lines; a second memory array having bit lines; a first sense amplifier connected to a first bit line of the first memory array and a first bit line of the second memory array; and a second sense amplifier connected to a second bit line of the first memory array and a second bit line of the second memory array. The second bit line of the first memory array is adjacent to the first bit line of the first memory array, and the second bit line of the second memory array is adjacent to the first bit line of the second memory array.

公开(公告)号：US12217790B2

公开(公告)日：2025-02-04

申请号：US18182696

申请日：2023-03-13

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chieh Lee ,  Chia-En Huang ,  Chun-Ying Lee ,  Yi-Ching Liu ,  Yih Wang ,  Rose Tseng ,  Yao-Jen Yang ,  Jonathan Tsung-Yung Chang

IPC: G11C11/16 ,  G11C5/06 ,  G11C11/408 ,  G11C11/4091

Abstract: A device includes a substrate, a first sense amplifier disposed on the substrate, a first word line driver disposed on the substrate and situated adjacent the first sense amplifier in the x-direction, and a first memory array disposed above the first sense amplifier and above the first word line driver in the z-direction. A plurality of first conductive segments extend alternately in the x-direction and the y-direction, and are disposed between the first memory array and the first sense amplifier and configured to electrically connect the first sense amplifier to a first bit line of the first memory array. A plurality of second conductive segments extend alternately in the x-direction and the y-direction, and are disposed between the first memory array and the first word line driver and configured to electrically connect the first word line driver to a first word line of the first memory array.

公开(公告)号：US20240371433A1

公开(公告)日：2024-11-07

申请号：US18772117

申请日：2024-07-13

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chieh Lee ,  Yi-Ching Liu ,  Chia-En Huang ,  Wen-Chang Cheng ,  Jonathan Tsung-Yung Chang

IPC: G11C11/4091 ,  H10B12/00

Abstract: A memory structure includes a first memory array having bit lines; a second memory array having bit lines; a first sense amplifier connected to a first bit line of the first memory array and a first bit line of the second memory array; and a second sense amplifier connected to a second bit line of the first memory array and a second bit line of the second memory array. The second bit line of the first memory array is adjacent to the first bit line of the first memory array, and the second bit line of the second memory array is adjacent to the first bit line of the second memory array.

公开(公告)号：US12063786B2

公开(公告)日：2024-08-13

申请号：US17726086

申请日：2022-04-21

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chieh Lee ,  Chia-En Huang ,  Yi-Ching Liu ,  Wen-Chang Cheng ,  Yih Wang

IPC: H10B51/20 ,  G11C5/04 ,  G11C5/06 ,  G11C11/22 ,  H10B51/10 ,  H10B51/30 ,  H10B51/40

CPC classification number: H10B51/20 ,  G11C5/04 ,  G11C5/063 ,  G11C11/223 ,  G11C11/2273 ,  H10B51/10 ,  H10B51/30 ,  H10B51/40 ,  G11C11/2255 ,  G11C11/2257

Abstract: In some embodiments, an integrated circuit (IC) device includes an active semiconductor layer, a circuitry formed within the active semiconductor layer, a region including conductive layers formed above the active semiconductor layer, and a memory module formed in the region. The memory device includes a three-dimensional array of memory cells, each adapted to store a weight value, and adapted to generate at each memory cell a signal indicative of a product between the stored weight value and an input signal applied to the memory cell. The memory module is further adapted to transmit the product signals from the memory cell simultaneously in the direction of the active semiconductor layer.

公开(公告)号：US20230282247A1

公开(公告)日：2023-09-07

申请号：US18316743

申请日：2023-05-12

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chieh Lee ,  Yi-Ching Liu ,  Chia-En Huang ,  Jen-Yuan Chang ,  Yih Wang

IPC: G11C5/06 ,  G11C5/02 ,  H01L23/48 ,  H10B12/00 ,  H10B61/00 ,  H10B63/00 ,  H10N50/01 ,  H10N50/80 ,  H10N70/00

CPC classification number: G11C5/06 ,  G11C5/025 ,  H01L23/481 ,  H10B12/00 ,  H10B61/00 ,  H10B63/84 ,  H10N50/01 ,  H10N50/80 ,  H10N70/011 ,  H10N70/821

Abstract: A memory device includes a first layer, wherein the first layer includes a first memory array, a first row decoder circuit, and a first column sensing circuit. The memory device includes a second layer disposed with respect to the first layer in a vertical direction. The second layer includes a first peripheral circuit operatively coupled to the first memory array, the first row decoder circuit, and the first column sensing circuit. The memory device includes a plurality of interconnect structures extending along the vertical direction. At least a first one of the plurality of interconnect structures operatively couples the second layer to the first layer.