公开(公告)号：US12068023B2

公开(公告)日：2024-08-20

申请号：US17643191

申请日：2021-12-08

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chieh Lee ,  Yi-Ching Liu ,  Chia-En Huang ,  Wen-Chang Cheng ,  Jonathan Tsung-Yung Chang

IPC: G11C8/00 ,  G11C11/4091 ,  H10B12/00

CPC classification number: G11C11/4091 ,  H10B12/09 ,  H10B12/50

Abstract: A memory structure includes a first memory array having bit lines; a second memory array having bit lines; a first sense amplifier connected to a first bit line of the first memory array and a first bit line of the second memory array; and a second sense amplifier connected to a second bit line of the first memory array and a second bit line of the second memory array. The second bit line of the first memory array is adjacent to the first bit line of the first memory array, and the second bit line of the second memory array is adjacent to the first bit line of the second memory array.

公开(公告)号：US12249390B2

公开(公告)日：2025-03-11

申请号：US18316743

申请日：2023-05-12

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chieh Lee ,  Yi-Ching Liu ,  Chia-En Huang ,  Jen-Yuan Chang ,  Yih Wang

IPC: G11C5/06 ,  G11C5/02 ,  H01L23/48 ,  H10B12/00 ,  H10B61/00 ,  H10B63/00 ,  H10N50/01 ,  H10N50/80 ,  H10N70/00

Abstract: A memory device includes a first layer, wherein the first layer includes a first memory array, a first row decoder circuit, and a first column sensing circuit. The memory device includes a second layer disposed with respect to the first layer in a vertical direction. The second layer includes a first peripheral circuit operatively coupled to the first memory array, the first row decoder circuit, and the first column sensing circuit. The memory device includes a plurality of interconnect structures extending along the vertical direction. At least a first one of the plurality of interconnect structures operatively couples the second layer to the first layer.

公开(公告)号：US12243589B2

公开(公告)日：2025-03-04

申请号：US17898733

申请日：2022-08-30

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Pei-Chun Liao ,  Yu-Kai Chang ,  Yi-Ching Liu ,  Yu-Ming Lin ,  Yih Wang ,  Chieh Lee

IPC: G11C16/26 ,  G11C16/08 ,  G11C16/32

Abstract: A memory device is provided, including a memory array, a driver circuit, and recover circuit. The memory array includes multiple memory cells. Each memory cell is coupled to a control line, a data line, and a source line and, during a normal operation, is configured to receive first and second voltage signals. The driver circuit is configured to output at least one of the first voltage signal or the second voltage signal to the memory cells. The recover circuit is configured to output, during a recover operation, a third voltage signal, through the driver circuit to at least one of the memory cells. The third voltage signal is configured to have a first voltage level that is higher than a highest level of the first voltage signal or the second voltage signal, or lower than a lowest level of the first voltage signal or the second voltage signal.

公开(公告)号：US20250024657A1

公开(公告)日：2025-01-16

申请号：US18350521

申请日：2023-07-11

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Wei-Hua Chen ,  Kuan-Chung Chiu ,  Chieh Lee ,  Chun-Ying Lee ,  Chia-En Huang ,  Yi-Ching Liu

IPC: H10B10/00 ,  H01L23/522 ,  H01L23/528 ,  H01L29/06 ,  H01L29/778 ,  H01L29/786

Abstract: A method includes depositing a metal to form a gate layer for a first memory cell in a metallization layer of the semiconductor device. The method includes forming a plurality of semiconductor channels separated from the gate layer by a gate oxide layer. The method includes defining a plurality of gates from the gate layer. The method includes interconnecting the plurality of gates and the plurality of semiconductor channels to form a memory cell, wherein the interconnection comprises a plurality of mezzanine levels.

公开(公告)号：US20230386577A1

公开(公告)日：2023-11-30

申请号：US17752662

申请日：2022-05-24

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chun-Ying Lee ,  Chia-En Huang ,  Chieh Lee

IPC: G11C16/08 ,  G11C16/04 ,  H01L27/11551 ,  H01L27/11578

CPC classification number: G11C16/08 ,  G11C16/0483 ,  H01L27/11551 ,  H01L27/11578

Abstract: A memory device includes a plurality of word lines (WLs). The memory device includes a plurality of drivers that are each configured to control a corresponding one of the plurality of WLs and each comprise a first transistor having a first conductive type and a second transistor having a second conductive type. The first transistor of a first one of the drivers is formed in a first well of a substrate, and the second transistor of the first driver is formed in a second well of the substrate. The first well is spaced apart from the second well.

公开(公告)号：US20230269931A1

公开(公告)日：2023-08-24

申请号：US17675838

申请日：2022-02-18

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Chieh Lee ,  Chia-En Huang ,  Chun-Ying Lee

IPC: H01L27/108 ,  H01L29/786 ,  H01L29/417 ,  H01L29/66

CPC classification number: H01L27/10814 ,  H01L29/78642 ,  H01L29/41733 ,  H01L27/10855 ,  H01L27/10873 ,  H01L29/66742 ,  H01L27/10885

Abstract: A semiconductor device includes a transistor that is disposed on a substrate. The transistor includes a gate electrode located over the substrate, a gate dielectric disposed on the gate electrode, a channel layer disposed on the gate dielectric, a first source/drain contact disposed on the channel layer and located on a side of the channel layer that is opposite to the substrate, and a second source/drain contact disposed on the channel layer and located on a side of the channel layer that faces the substrate. One of the gate dielectric and the channel layer at least partially surrounds the other one of the gate dielectric and the channel layer. A region of the channel layer between the first source/drain contact and the second source/drain contact is elongated in a direction perpendicular to the substrate.

公开(公告)号：US20250107072A1

公开(公告)日：2025-03-27

申请号：US18472862

申请日：2023-09-22

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Ji-Kuan Lee ,  Chieh Lee ,  Chia-En Huang ,  Yao-Jen Yang

IPC: H10B12/00

Abstract: A memory device includes a substrate; a plurality of metallization layers disposed over the substrate; a plurality of memory cells, each of the plurality of memory cells including a transistor and a capacitor; and a bit line coupled to a corresponding set of the plurality of memory cells. The bit line comprises at least a first conductor structure and a second conductor structure that extend along a first lateral direction and are disposed in a first one of the plurality of metallization layers. The first conductor structure and the second conductor structure are physically spaced from each other, but are electrically coupled to each other through conductor structures disposed in one or more of the plurality of metallization layers.

公开(公告)号：US20240257877A1

公开(公告)日：2024-08-01

申请号：US18632856

申请日：2024-04-11

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chun-Ying Lee ,  Chia-En Huang ,  Chieh Lee

IPC: G11C16/08 ,  G11C16/04 ,  H10B41/20 ,  H10B43/20

CPC classification number: G11C16/08 ,  G11C16/0483 ,  H10B41/20 ,  H10B43/20

Abstract: A memory device includes a plurality of word lines (WLs) above a substrate; a plurality of memory strings laterally isolated from each other, each of the plurality of memory strings being operatively coupled to a respective subset of the plurality of WLs; and a plurality of drivers, each of the plurality of drivers being configured to control a corresponding one of the plurality of WLs and including a first transistor having a first conductive type and a second transistor having a second conductive type opposite to the first conductive type.

公开(公告)号：US20230067423A1

公开(公告)日：2023-03-02

申请号：US17461332

申请日：2021-08-30

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chieh Lee ,  Yi-Ching Liu ,  Chia-En Huang ,  Chang Jen-Yuan ,  Yih Wang

IPC: G11C5/06 ,  G11C5/02 ,  H01L23/48 ,  H01L27/24 ,  H01L45/00 ,  H01L27/108 ,  H01L27/22 ,  H01L43/02 ,  H01L43/12

Abstract: A memory device includes a first layer, wherein the first layer includes a first memory array, a first row decoder circuit, and a first column sensing circuit. The memory device includes a second layer disposed with respect to the first layer in a vertical direction. The second layer includes a first peripheral circuit operatively coupled to the first memory array, the first row decoder circuit, and the first column sensing circuit. The memory device includes a plurality of interconnect structures extending along the vertical direction. At least a first one of the plurality of interconnect structures operatively couples the second layer to the first layer.

公开(公告)号：US20240365556A1

公开(公告)日：2024-10-31

申请号：US18769532

申请日：2024-07-11

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chieh Lee ,  Chia-En Huang ,  Yi-Ching Liu ,  Wen-Chang Cheng ,  Yih Wang

IPC: H10B51/20 ,  G11C5/04 ,  G11C5/06 ,  G11C11/22 ,  H10B51/10 ,  H10B51/30 ,  H10B51/40

CPC classification number: H10B51/20 ,  G11C5/04 ,  G11C5/063 ,  G11C11/223 ,  G11C11/2273 ,  H10B51/10 ,  H10B51/30 ,  H10B51/40 ,  G11C11/2255 ,  G11C11/2257

Abstract: In some embodiments, an integrated circuit (IC) device includes an active semiconductor layer, a circuitry formed within the active semiconductor layer, a region including conductive layers formed in a back-end-of-line (BEOL) layer above the active semiconductor layer, and a memory module formed in the BEOL layer. The memory device includes a three-dimensional array of memory cells, each adapted to store a weight value, and adapted to generate at each memory cell a signal indicative of a product between the stored weight value and an input signal applied to the memory cell. The memory module is further adapted to transmit the product signals from the memory cell simultaneously in the direction of the active semiconductor layer.