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公开(公告)号：US12041860B2
公开(公告)日：2024-07-16
申请号：US17581153
申请日：2022-01-21
Inventor： Yu-Der Chih , Wen-Zhang Lin , Yun-Sheng Chen , Jonathan Tsung-Yung Chang , Chrong-Jung Lin , Ya-Chin King , Cheng-Jun Lin , Wang-Yi Lee
CPC classification number: H10N70/021 , H10B63/80 , H10N70/063 , H10N70/066 , H10N70/068 , H10N70/841
Abstract: A resistive memory device includes a bottom electrode, a top electrode and a resistance changing element. The top electrode is disposed above and spaced apart from the bottom electrode, and has a downward protrusion aligned with the bottom electrode. The resistance changing element covers side and bottom surfaces of the downward protrusion.
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公开(公告)号：US11943936B2
公开(公告)日：2024-03-26
申请号：US17400615
申请日：2021-08-12
Inventor： Yu-Der Chih , May-Be Chen , Yun-Sheng Chen , Jonathan Tsung-Yung Chang , Wen Zhang Lin , Chrong Jung Lin , Ya-Chin King , Chieh Lee , Wang-Yi Lee
CPC classification number: H10B63/30 , H01L29/401 , H01L29/785
Abstract: A semiconductor device and a method of manufacturing the same are provided. The semiconductor device includes a first transistor, a first resistive random access memory (RRAM) resistor, and a second RRAM resistor. The first resistor includes a first resistive material layer, a first electrode shared by the second resistor, and a second electrode. The second resistor includes the first electrode, a second resistive material layer, and a third electrode. The first electrode is electrically coupled to the first transistor.
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公开(公告)号：US12051466B2
公开(公告)日：2024-07-30
申请号：US18301745
申请日：2023-04-17
Inventor： Yu-Der Chih , Jonathan Tsung-Yung Chang , Yun-Sheng Chen , Maybe Chen , Ya-chin King , Wen Zhang Lin , Chrong Jung Lin , Hsin-Yuan Yu
CPC classification number: G11C13/004 , G11C13/0069 , H10B63/30 , H10N70/253 , G11C2013/0045 , G11C2013/0078
Abstract: Disclosed herein are related to a memory cell including one or more programmable resistors and a control transistor. In one aspect, a programmable resistor includes a gate structure and one or more source/drain structures for forming a transistor. A resistance of the programmable resistor may be set by applying a voltage to the gate structure, while the control transistor is enabled. Data stored by the programmable resistor can be read by sensing current through the programmable resistor, while the control transistor is disabled. In one aspect, the one or more programmable resistors and the control transistor are implemented by same type of components, allowing the memory cell to be formed in a compact manner through a simplified the fabrication process.
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Patent Agency Ranking
公开(公告)号：US11646079B2
公开(公告)日：2023-05-09
申请号：US17337781
申请日：2021-06-03
Inventor： Yu-Der Chih , Maybe Chen , Yun-Sheng Chen , Wen Zhang Lin , Jonathan Tsung-Yung Chang , Chrong Jung Lin , Ya-Chin King , Hsin-Yuan Yu
CPC classification number: G11C13/004 , G11C13/0069 , H01L27/2436 , H01L45/1206 , G11C2013/0045 , G11C2013/0078
Abstract: Disclosed herein are related to a memory cell including one or more programmable resistors and a control transistor. In one aspect, a programmable resistor includes a gate structure and one or more source/drain structures for forming a transistor. A resistance of the programmable resistor may be set by applying a voltage to the gate structure, while the control transistor is enabled. Data stored by the programmable resistor can be read by sensing current through the programmable resistor, while the control transistor is disabled. In one aspect, the one or more programmable resistors and the control transistor are implemented by same type of components, allowing the memory cell to be formed in a compact manner through a simplified the fabrication process.
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公开(公告)号：US20240407159A1
公开(公告)日：2024-12-05
申请号：US18326228
申请日：2023-05-31
Inventor： Yu-Der Chih , Ya-Chin King , Chrong Lin , Jonathan Tsung-Yung Chang , Yun-Sheng Chen , May-Be Chen , Hsin-Yuan Yu
IPC: H10B20/25
Abstract: A memory device is disclosed. The memory device includes a memory cell comprising: a transistor; and a plurality of pairs of resistors coupled to the transistor in series, each of the pairs of resistors including a first resistor and a second resistor. The transistor is formed along a major surface of a substrate. At least a first one of the pairs of resistors are formed in a first one of a plurality of metallization layers disposed above the transistor. At least a second one of the pairs of resistors are formed in a second one of the plurality of metallization layers, the second metallization layer being disposed above the first metallization layer.
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公开(公告)号：US20230253040A1
公开(公告)日：2023-08-10
申请号：US18301745
申请日：2023-04-17
Inventor： Yu-Der Chih , Jonathan Tsung-Yung Chang , Yun-Sheng Chen , May-Be Chen , Ya-Chin King , Wen Zhang Lin , Chrong Lin , Hsin-Yuan Yu
CPC classification number: G11C13/004 , G11C13/0069 , H10B63/30 , H10N70/253 , G11C2013/0045 , G11C2013/0078
Abstract: Disclosed herein are related to a memory cell including one or more programmable resistors and a control transistor. In one aspect, a programmable resistor includes a gate structure and one or more source/drain structures for forming a transistor. A resistance of the programmable resistor may be set by applying a voltage to the gate structure, while the control transistor is enabled. Data stored by the programmable resistor can be read by sensing current through the programmable resistor, while the control transistor is disabled. In one aspect, the one or more programmable resistors and the control transistor are implemented by same type of components, allowing the memory cell to be formed in a compact manner through a simplified the fabrication process.
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公开(公告)号：US20220068378A1
公开(公告)日：2022-03-03
申请号：US17337781
申请日：2021-06-03
Inventor： Yu-Der Chih , Maybe Chen , Yun-Sheng Chen , Wen Zhang Lin , Jonathan Tsung-Yung Chang , Chrong Jung Lin , Ya-Chin King , Hsin-Yuan Yu
Abstract: Disclosed herein are related to a memory cell including one or more programmable resistors and a control transistor. In one aspect, a programmable resistor includes a gate structure and one or more source/drain structures for forming a transistor. A resistance of the programmable resistor may be set by applying a voltage to the gate structure, while the control transistor is enabled. Data stored by the programmable resistor can be read by sensing current through the programmable resistor, while the control transistor is disabled. In one aspect, the one or more programmable resistors and the control transistor are implemented by same type of components, allowing the memory cell to be formed in a compact manner through a simplified the fabrication process.
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公开(公告)号：US20240355388A1
公开(公告)日：2024-10-24
申请号：US18758901
申请日：2024-06-28
Inventor： Yu-Der Chih , Jonathan Tsung-Yung Chang , Yun-Sheng Chen , Maybe Chen , Ya-Chin King , Wen Zhang Lin , Chrong Jung Lin , Hsin-Yuan Yu
CPC classification number: G11C13/004 , G11C13/0069 , H10B63/30 , H10N70/253 , G11C2013/0045 , G11C2013/0078
Abstract: Disclosed herein are related to a memory cell including one or more programmable resistors and a control transistor. In one aspect, a programmable resistor includes a gate structure and one or more source/drain structures for forming a transistor. A resistance of the programmable resistor may be set by applying a voltage to the gate structure, while the control transistor is enabled. Data stored by the programmable resistor can be read by sensing current through the programmable resistor, while the control transistor is disabled. In one aspect, the one or more programmable resistors and the control transistor are implemented by same type of components, allowing the memory cell to be formed in a compact manner through a simplified the fabrication process.
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