-
公开(公告)号：US20240407159A1
公开(公告)日：2024-12-05
申请号：US18326228
申请日：2023-05-31
Inventor： Yu-Der Chih , Ya-Chin King , Chrong Lin , Jonathan Tsung-Yung Chang , Yun-Sheng Chen , May-Be Chen , Hsin-Yuan Yu
IPC: H10B20/25
Abstract: A memory device is disclosed. The memory device includes a memory cell comprising: a transistor; and a plurality of pairs of resistors coupled to the transistor in series, each of the pairs of resistors including a first resistor and a second resistor. The transistor is formed along a major surface of a substrate. At least a first one of the pairs of resistors are formed in a first one of a plurality of metallization layers disposed above the transistor. At least a second one of the pairs of resistors are formed in a second one of the plurality of metallization layers, the second metallization layer being disposed above the first metallization layer.
-
公开(公告)号：US20210313472A1
公开(公告)日：2021-10-07
申请号：US17349921
申请日：2021-06-17
Inventor： Jiun Shiung Wu , Ya-Chin King , Chrong-Jung Lin
IPC: H01L29/788 , H01L27/11519 , H01L27/11524 , H01L27/11526
Abstract: A non-volatile memory cell is described. The non-volatile memory cell includes a substrate, insulators, a floating gate and a control gate. The substrate has a first fin and a second fin, wherein the second fin is located at a first side of the first fin and a conductive type of the second fin is different from that of the first fin. The insulators are located over the substrate, wherein the first fin and the second fin are respectively located between the insulators. The floating gate is located over the first fin, the insulators and the second fin. The control gate includes the second fin.
-
公开(公告)号：US20240404611A1
公开(公告)日：2024-12-05
申请号：US18328091
申请日：2023-06-02
Applicant: Taiwan Semiconductor Manufacturing Company, Ltd. , College of Semiconductor Research, National Tsing Hua University
Inventor： Chrong Jung Lin , Ya-Chin King , Li-Yu Wang
Abstract: A The memory device includes a memory array comprising a plurality of one-time-programmable (OTP) memory cells. Each of the plurality of OTP memory cells comprises: a select transistor; a diode; and a conductor fuse. The diode and the conductor fuse are coupled in series, with the select transistor coupled to a common node between the diode and the conductor fuse.
-
公开(公告)号：US20230253040A1
公开(公告)日：2023-08-10
申请号：US18301745
申请日：2023-04-17
Inventor： Yu-Der Chih , Jonathan Tsung-Yung Chang , Yun-Sheng Chen , May-Be Chen , Ya-Chin King , Wen Zhang Lin , Chrong Lin , Hsin-Yuan Yu
CPC classification number: G11C13/004 , G11C13/0069 , H10B63/30 , H10N70/253 , G11C2013/0045 , G11C2013/0078
Abstract: Disclosed herein are related to a memory cell including one or more programmable resistors and a control transistor. In one aspect, a programmable resistor includes a gate structure and one or more source/drain structures for forming a transistor. A resistance of the programmable resistor may be set by applying a voltage to the gate structure, while the control transistor is enabled. Data stored by the programmable resistor can be read by sensing current through the programmable resistor, while the control transistor is disabled. In one aspect, the one or more programmable resistors and the control transistor are implemented by same type of components, allowing the memory cell to be formed in a compact manner through a simplified the fabrication process.
-
公开(公告)号：US20220252989A1
公开(公告)日：2022-08-11
申请号：US17560039
申请日：2021-12-22
Inventor： Yu-Der Chih , May-Be Chen , Ya-Chin King , Chrong Jung Lin , Burn Jeng Lin , Bo Yu Lin
IPC: G03F7/20 , H01L21/66 , H01L21/027
Abstract: A semiconductor fabrication apparatus and a method of using the same are disclosed. In one aspect, the apparatus includes a holder configured to place a substrate and a radiation source configured to provide radiation to transfer a pattern onto the substrate. The apparatus also includes a plurality of sensing devices configured to provide a reference signal based on an intensity of the radiation when the substrate is not present. The apparatus further includes a controller, operatively coupled to the plurality of sensing devices, configured to adjust the intensity of the radiation based on the reference signal.
-
Patent Agency Ranking
公开(公告)号：US20220068378A1
公开(公告)日：2022-03-03
申请号：US17337781
申请日：2021-06-03
Inventor： Yu-Der Chih , Maybe Chen , Yun-Sheng Chen , Wen Zhang Lin , Jonathan Tsung-Yung Chang , Chrong Jung Lin , Ya-Chin King , Hsin-Yuan Yu
Abstract: Disclosed herein are related to a memory cell including one or more programmable resistors and a control transistor. In one aspect, a programmable resistor includes a gate structure and one or more source/drain structures for forming a transistor. A resistance of the programmable resistor may be set by applying a voltage to the gate structure, while the control transistor is enabled. Data stored by the programmable resistor can be read by sensing current through the programmable resistor, while the control transistor is disabled. In one aspect, the one or more programmable resistors and the control transistor are implemented by same type of components, allowing the memory cell to be formed in a compact manner through a simplified the fabrication process.
-
公开(公告)号：US20240355388A1
公开(公告)日：2024-10-24
申请号：US18758901
申请日：2024-06-28
Inventor： Yu-Der Chih , Jonathan Tsung-Yung Chang , Yun-Sheng Chen , Maybe Chen , Ya-Chin King , Wen Zhang Lin , Chrong Jung Lin , Hsin-Yuan Yu
CPC classification number: G11C13/004 , G11C13/0069 , H10B63/30 , H10N70/253 , G11C2013/0045 , G11C2013/0078
Abstract: Disclosed herein are related to a memory cell including one or more programmable resistors and a control transistor. In one aspect, a programmable resistor includes a gate structure and one or more source/drain structures for forming a transistor. A resistance of the programmable resistor may be set by applying a voltage to the gate structure, while the control transistor is enabled. Data stored by the programmable resistor can be read by sensing current through the programmable resistor, while the control transistor is disabled. In one aspect, the one or more programmable resistors and the control transistor are implemented by same type of components, allowing the memory cell to be formed in a compact manner through a simplified the fabrication process.
-
公开(公告)号：US12249662B2
公开(公告)日：2025-03-11
申请号：US17749382
申请日：2022-05-20
Inventor： Ya-Chin King , Chrong Jung Lin , Burn Jeng Lin , Shi-Jiun Wang
IPC: H01L31/02 , H01J37/244 , H01L31/18
Abstract: A device includes a detector, a sensing pad, a ring structure, a control circuit, a first transistor, and a second transistor. The sensing pad is electrically connected to the detector. The ring structure is over the sensing pad and includes an upper conductive ring and a lower conductive ring between the upper conductive ring and the sensing pad. The first transistor interconnects the upper conductive ring and the control circuit. The second transistor interconnects the lower conductive ring and the control circuit.
-
公开(公告)号：US20240395641A1
公开(公告)日：2024-11-28
申请号：US18322046
申请日：2023-05-23
Inventor： Ya-Chin King , Chrong Jung LIN , Burn Jeng LIN , Wei CHANG
IPC: H01L21/66
Abstract: A device in a chamber is provided. The device comprises at least one die. The at least one die comprise a first voltage generator, a dielectric layer and a first voltage regulator circuit. The first voltage generator is charged to have a first induced voltage by induced charges generated in response to a first voltage of a first electrode of a chuck in the chamber. The dielectric layer surrounds the first voltage generator to isolate the first voltage generator from the first electrode. The first voltage regulator circuit is coupled to the first voltage generator to receive the first induced voltage and generates a first power supply voltage according to the first induced voltage for a first circuit in the device.
-
公开(公告)号：US12009177B2
公开(公告)日：2024-06-11
申请号：US17171939
申请日：2021-02-09
Inventor： Ya-Chin King , Chrong-Jung Lin , Burn-Jeng Lin , Chien-Ping Wang , Shao-Hua Wang , Chun-Lin Chang , Li-Jui Chen
IPC: H01J37/304 , G03F7/00 , H01J37/30 , H01L27/144 , H01L31/02 , H01L31/113 , H01L31/18
CPC classification number: H01J37/304 , G03F7/70516 , G03F7/7055 , G03F7/70616 , H01J37/3002 , H01L27/1446 , H01L31/02005 , H01L31/1136 , H01L31/18
Abstract: A method includes applying a first voltage to a source of a first transistor of a detector unit of a semiconductor detector in a test wafer and applying a second voltage to a gate of the first transistor and a drain of a second transistor of the detector unit. The first transistor is coupled to the second transistor in series, and the first voltage is higher than the second voltage. A pre-exposure reading operation is performed to the detector unit. Light of an exposure apparatus is illuminated to a gate of the second transistor after applying the first and second voltages. A post-exposure reading operation is performed to the detector unit. Data of the pre-exposure reading operation is compared with the post-exposure reading operation. An intensity of the light is adjusted based on the compared data of the pre-exposure reading operation and the post-exposure reading operation.
-
-
-
-
-
-
-
-
-
Search Results
16
records
(took 0.017 seconds)
