公开(公告)号：US20170309569A1

公开(公告)日：2017-10-26

申请号：US15647467

申请日：2017-07-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Raheel Azmat ,  Sengupta RWIK ,  Su-Hyeon KIM ,  Chul-Hong PARK ,  Jae-Hyoung LIM

IPC: H01L23/528 ,  H01L29/66 ,  H01L29/165 ,  H01L29/161 ,  H01L29/16 ,  H01L29/06 ,  H01L21/285 ,  H01L27/092 ,  H01L21/8238 ,  H01L29/78 ,  H01L29/08

CPC classification number: H01L23/5286 ,  H01L21/28518 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823871 ,  H01L21/823878 ,  H01L27/0207 ,  H01L27/092 ,  H01L27/0924 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/7848

Abstract: A logic semiconductor device includes a plurality of active patterns extending in a horizontal direction and being spaced apart from each other in a vertical direction, an isolation layer defining the active patterns, a plurality of gate patterns extending in the vertical direction on the active patterns and the isolation layer, the gate patterns being spaced apart from each other in the horizontal direction, a plurality of lower wirings extending in the horizontal direction over the gate patterns, a plurality of upper wirings extending in the vertical direction over the lower wirings, a through contact connecting at least one upper wiring of the upper wirings and at least one gate pattern of the gate patterns, the through contact extending from a bottom surface of the upper wiring to a position under a bottom surface of one of the lower wirings relative to the active patterns.

公开(公告)号：US20230015367A1

公开(公告)日：2023-01-19

申请号：US17944379

申请日：2022-09-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Raheel Azmat ,  Sidharth Rastogi ,  Chul-hong Park ,  Jae-seok Yang ,  Kwan-young Chun

IPC: G06F30/327 ,  H01L27/02 ,  G06F30/398

Abstract: An integrated circuit including a standard cell includes: a plurality of first wells extending in a first horizontal direction with a first width and of a first conductivity type; and a plurality of second wells extending in the first horizontal direction with a second width and having a second conductivity type, wherein the plurality of first wells and the plurality of second wells are alternately arranged in a second horizontal direction that is orthogonal to the first horizontal direction, and when m and n are integers greater than or equal to 3, the standard cell has a length in the second horizontal direction, the length being equal to a sum of m times a half of the first width and n times a half of the second width.

公开(公告)号：US11316032B2

公开(公告)日：2022-04-26

申请号：US16887331

申请日：2020-05-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Deepak Sharma ,  Hyun-jong Lee ,  Raheel Azmat ,  Chul-hong Park ,  Sang-jun Park

IPC: H01L29/66 ,  H01L27/088 ,  H01L27/02 ,  H01L23/528 ,  H01L27/092 ,  H01L21/8238

Abstract: Provided is an integrated circuit including at least one cell, the at least one cell includes first and second active regions spaced apart from each other, a dummy region disposed between the first and second active regions, at least one first active fin disposed in the first active region and extending in a first direction, at least one second active fin extending along the first direction over the entire length of the second active region, and an active gate line extending in a second direction that is substantially perpendicular to the first direction, wherein the active gate line vertically overlaps the first active region and the dummy region and does not vertically overlap the second active region.

公开(公告)号：US20190252380A1

公开(公告)日：2019-08-15

申请号：US16390431

申请日：2019-04-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Deepak SHARMA ,  Hyun-jong Lee ,  Raheel Azmat ,  Chul-hong Park ,  Sang-jun Park

IPC: H01L27/088 ,  H01L27/092 ,  H01L29/66 ,  H01L27/02 ,  H01L23/528

CPC classification number: H01L27/0886 ,  H01L21/823828 ,  H01L23/528 ,  H01L27/0207 ,  H01L27/0924 ,  H01L29/6681

Abstract: Provided is an integrated circuit including at least one cell, the at least one cell includes first and second active regions spaced apart from each other, a dummy region disposed between the first and second active regions, at least one first active fin disposed in the first active region and extending in a first direction, at least one second active fin extending along the first direction over the entire length of the second active region, and an active gate line extending in a second direction that is substantially perpendicular to the first direction, wherein the active gate line vertically overlaps the first active region and the dummy region and does not vertically overlap the second active region.

公开(公告)号：US09929180B2

公开(公告)日：2018-03-27

申请号：US15496015

申请日：2017-04-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Raheel Azmat ,  Rwik Sengupta ,  Chulhong Park ,  Kwanyoung Chun

IPC: H01L27/118 ,  H01L23/535 ,  H01L29/06

CPC classification number: H01L27/11807 ,  H01L23/535 ,  H01L23/5384 ,  H01L27/0207 ,  H01L29/0649 ,  H01L2924/0002 ,  H03K19/1736 ,  H01L2924/00

Abstract: Provided is a semiconductor device including a substrate with a plurality of logic cells, transistors provided in the plurality of logic cells, contact plugs connected to electrodes of the transistors, first via plugs in contact with top surfaces of the contact plugs, and first wires in contact with top surfaces of the first via plugs. The first wires may include a common conductive line connected to the plurality of logic cells through the contact plugs, and all of the first wires may be shaped like a straight line extending parallel to a specific direction.

公开(公告)号：US09443851B2

公开(公告)日：2016-09-13

申请号：US14534536

申请日：2014-11-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Rwik Sengupta ,  Raheel Azmat

IPC: H01L27/088 ,  H01L21/8234 ,  H01L27/02 ,  H01L21/768

CPC classification number: H01L27/0886 ,  H01L21/76895 ,  H01L21/823431 ,  H01L21/823475 ,  H01L27/0207

Abstract: Semiconductor devices and methods of forming the same are provided. The semiconductor devices may include a finFET, a metal routing layer, a first local interconnect layer, and a second local interconnect layer. The finFET may include a channel, a first source/drain region, a second source/drain region, and a gate stack. The metal routing layer may be separated from the finFET in a vertical direction. The first local interconnect layer may include a first local interconnect that contacts a first metal route in the metal routing layer and that electrically connects to the first source/drain region. The second local interconnect layer may include a second local interconnect that contacts a second metal route in the metal routing layer and that electrically connects to the gate stack.

Abstract translation: 提供了半导体器件及其形成方法。 半导体器件可以包括finFET，金属布线层，第一局部互连层和第二局部互连层。 finFET可以包括沟道，第一源极/漏极区域，第二源极/漏极区域和栅极堆叠。 金属布线层可以在垂直方向上与finFET分离。 第一局部互连层可以包括接触金属布线层中的第一金属路径并且电连接到第一源极/漏极区的第一局部互连。 第二局部互连层可以包括接触金属布线层中的第二金属路径并且电连接到栅极堆叠的第二局部互连。

公开(公告)号：US09418990B2

公开(公告)日：2016-08-16

申请号：US14736441

申请日：2015-06-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Raheel Azmat ,  Sharma Deepak ,  Chulhong Park

IPC: H01L27/02 ,  H01L27/088

CPC classification number: H01L27/0886 ,  H01L21/823431 ,  H01L21/823821 ,  H01L23/5226 ,  H01L23/528 ,  H01L27/0207 ,  H01L27/088 ,  H01L27/0924 ,  H01L27/11807 ,  H01L29/0649 ,  H01L29/0847 ,  H01L2027/11829 ,  H01L2027/11875

Abstract: A semiconductor device, and a method of manufacturing the same, includes first and second gate structures extending in a first direction and spaced apart from each other in a second direction intersecting the first direction, a dummy gate structure provided between the first and second gate structures, a first source/drain region between the first gate structure and the dummy gate structure, a second source/drain region between the second gate structure and the dummy gate structure, a connection contact provided on the dummy gate structure, and a common conductive line provided on the connection contact. The dummy gate structure extends in the first direction. The connection contact extends in the second direction to connect the first source/drain region to the second source/drain region. The common conductive line configured to a voltage to the first and second source/drain regions through the connection contact.

Abstract translation: 半导体器件及其制造方法包括在与第一方向相交的第二方向上在第一方向上延伸并彼此间隔开的第一和第二栅极结构，设置在第一和第二栅极结构之间的虚拟栅极结构 在第一栅极结构和伪栅极结构之间的第一源极/漏极区域，在第二栅极结构和伪栅极结构之间的第二源极/漏极区域，设置在虚拟栅极结构上的连接接触点以及公共导线 提供在连接接点上。 虚拟栅极结构沿第一方向延伸。 连接触头沿第二方向延伸以将第一源极/漏极区域连接到第二源极/漏极区域。 所述公共导线被配置为通过所述连接接触到所述第一和第二源极/漏极区域的电压。

公开(公告)号：US09324715B2

公开(公告)日：2016-04-26

申请号：US14504075

申请日：2014-10-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Raheel Azmat ,  Rwik Sengupta ,  Chulhong Park ,  Kwanyoung Chun

IPC: H01L27/092 ,  H01L27/02 ,  H01L21/8238

CPC classification number: H01L27/092 ,  H01L21/823828 ,  H01L21/823871 ,  H01L27/0207

Abstract: A semiconductor device includes a substrate including PMOSFET and NMOSFET regions. First and second gate electrodes are provided on the PMOSFET region, and third and fourth gate electrodes are provided on the NMOSFET region. A connection contact is provided to connect the second gate electrode with the third gate electrode, and a connection line is provided on the connection contact to cross the connection contact and connect the first gate electrode to the fourth gate electrode.

Abstract translation: 半导体器件包括包括PMOSFET和NMOSFET区域的衬底。 第一和第二栅电极设置在PMOSFET区上，第三和第四栅电极设置在NMOSFET区上。 提供连接触点以连接第二栅电极和第三栅电极，并且连接线设置在连接触头上以与连接触头交叉，并将第一栅电极连接到第四栅电极。

公开(公告)号：US11688740B2

公开(公告)日：2023-06-27

申请号：US17740900

申请日：2022-05-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Taehyung Kim ,  Jinwoo Jeong ,  Jiwook Kwon ,  Raheel Azmat ,  Kwanyoung Chun

IPC: H01L27/092 ,  H01L23/528 ,  H01L27/11 ,  H01L29/06 ,  H01L29/423 ,  H01L29/78 ,  H01L29/66 ,  H01L29/786 ,  H01L21/02 ,  H01L21/8238 ,  H01L27/02 ,  H10B10/00

CPC classification number: H01L27/0922 ,  H01L21/02532 ,  H01L21/02603 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823871 ,  H01L23/5286 ,  H01L27/0207 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66742 ,  H01L29/7848 ,  H01L29/78618 ,  H01L29/78696 ,  H10B10/125

Abstract: A semiconductor device including a substrate; first to third active patterns on an upper portion of the substrate, the active patterns being sequentially arranged in a first direction and extending in a second direction crossing the first direction; first to third power rails respectively connected to the first to third active patterns, wherein a width of the second active pattern in the first direction is at least two times a width of the first active pattern in the first direction and is at least two times a width of the third active pattern in the first direction, the first active pattern is not vertically overlapped with the first power rail, the second active pattern is vertically overlapped with the second power rail, and the third active pattern is not vertically overlapped with the third power rail.

公开(公告)号：US11282836B2

公开(公告)日：2022-03-22

申请号：US16894045

申请日：2020-06-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Deepak Sharma ,  Hyun-jong Lee ,  Raheel Azmat ,  Chul-hong Park ,  Sang-jun Park

IPC: H01L29/76 ,  H01L29/94 ,  H01L27/088 ,  H01L27/02 ,  H01L23/528 ,  H01L27/092 ,  H01L29/66 ,  H01L21/8238

Abstract: Provided is an integrated circuit including at least one cell, the at least one cell includes first and second active regions spaced apart from each other, a dummy region disposed between the first and second active regions, at least one first active fin disposed in the first active region and extending in a first direction, at least one second active fin extending along the first direction over the entire length of the second active region, and an active gate line extending in a second direction that is substantially perpendicular to the first direction, wherein the active gate line vertically overlaps the first active region and the dummy region and does not vertically overlap the second active region.