公开(公告)号：US20170117223A1

公开(公告)日：2017-04-27

申请号：US15188743

申请日：2016-06-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Raheel Azmat ,  Sengupta RWIK ,  Su-Hyeon KIM ,  Chul-Hong PARK ,  Jae-Hyoung LIM

IPC: H01L23/528 ,  H01L29/08 ,  H01L29/161 ,  H01L29/16 ,  H01L21/285 ,  H01L29/78 ,  H01L29/06 ,  H01L21/8238 ,  H01L29/66 ,  H01L27/092 ,  H01L29/165

CPC classification number: H01L23/5286 ,  H01L21/28518 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823871 ,  H01L21/823878 ,  H01L27/0207 ,  H01L27/092 ,  H01L27/0924 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/7848

Abstract: A logic semiconductor device includes a plurality of active patterns extending in a horizontal direction and being spaced apart from each other in a vertical direction, an isolation layer defining the active patterns, a plurality of gate patterns extending in the vertical direction on the active patterns and the isolation layer, the gate patterns being spaced apart from each other in the horizontal direction, a plurality of lower wirings extending in the horizontal direction over the gate patterns, a plurality of upper wirings extending in the vertical direction over the lower wirings, a through contact connecting at least one upper wiring of the upper wirings and at least one gate pattern of the gate patterns, the through contact extending from a bottom surface of the upper wiring to a position under a bottom surface of one of the lower wirings relative to the active patterns.

公开(公告)号：US20240234558A9

公开(公告)日：2024-07-11

申请号：US18201878

申请日：2023-05-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jongmin SHIN ,  Wook Hyun KWON ,  Su-Hyeon KIM ,  Jun Mo PARK ,  Kyu Bong CHOI

IPC: H01L29/775 ,  H01L27/088 ,  H01L29/06 ,  H01L29/423

CPC classification number: H01L29/775 ,  H01L27/088 ,  H01L29/0673 ,  H01L29/42392

Abstract: A semiconductor device includes a first active pattern including a first lower pattern and first sheet patterns; a second active pattern including a second lower pattern and second sheet patterns, a height of the second lower pattern being smaller than a height of the first lower pattern; a first gate structure on the first lower pattern; a second gate structure on the second lower pattern; a first source/drain pattern on the first lower pattern and connected to the first sheet patterns; and a second source/drain pattern on the second lower pattern and connected to the second sheet patterns, wherein a width of an upper surface of the first lower pattern is different from a width of an upper surface of the second lower pattern, and wherein a number of first sheet patterns is different from a number of second sheet patterns.

公开(公告)号：US20170309569A1

公开(公告)日：2017-10-26

申请号：US15647467

申请日：2017-07-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Raheel Azmat ,  Sengupta RWIK ,  Su-Hyeon KIM ,  Chul-Hong PARK ,  Jae-Hyoung LIM

IPC: H01L23/528 ,  H01L29/66 ,  H01L29/165 ,  H01L29/161 ,  H01L29/16 ,  H01L29/06 ,  H01L21/285 ,  H01L27/092 ,  H01L21/8238 ,  H01L29/78 ,  H01L29/08

CPC classification number: H01L23/5286 ,  H01L21/28518 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823871 ,  H01L21/823878 ,  H01L27/0207 ,  H01L27/092 ,  H01L27/0924 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/7848

Abstract: A logic semiconductor device includes a plurality of active patterns extending in a horizontal direction and being spaced apart from each other in a vertical direction, an isolation layer defining the active patterns, a plurality of gate patterns extending in the vertical direction on the active patterns and the isolation layer, the gate patterns being spaced apart from each other in the horizontal direction, a plurality of lower wirings extending in the horizontal direction over the gate patterns, a plurality of upper wirings extending in the vertical direction over the lower wirings, a through contact connecting at least one upper wiring of the upper wirings and at least one gate pattern of the gate patterns, the through contact extending from a bottom surface of the upper wiring to a position under a bottom surface of one of the lower wirings relative to the active patterns.

公开(公告)号：US20240136430A1

公开(公告)日：2024-04-25

申请号：US18201878

申请日：2023-05-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jongmin SHIN ,  Wook Hyun KWON ,  Su-Hyeon KIM ,  Jun Mo PARK ,  Kyu Bong CHOI

IPC: H01L29/775 ,  H01L27/088 ,  H01L29/06 ,  H01L29/423

CPC classification number: H01L29/775 ,  H01L27/088 ,  H01L29/0673 ,  H01L29/42392

Abstract: A semiconductor device includes a first active pattern including a first lower pattern and first sheet patterns; a second active pattern including a second lower pattern and second sheet patterns, a height of the second lower pattern being smaller than a height of the first lower pattern; a first gate structure on the first lower pattern; a second gate structure on the second lower pattern; a first source/drain pattern on the first lower pattern and connected to the first sheet patterns; and a second source/drain pattern on the second lower pattern and connected to the second sheet patterns, wherein a width of an upper surface of the first lower pattern is different from a width of an upper surface of the second lower pattern, and wherein a number of first sheet patterns is different from a number of second sheet patterns.