公开(公告)号：US20180096935A1

公开(公告)日：2018-04-05

申请号：US15497283

申请日：2017-04-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyo-Jin KIM ,  Chang-Hwa KIM ,  Hwi-Chan JUN ,  Chul-Hong PARK ,  Jae-Seok YANG ,  Kwan-Young CHUN

IPC: H01L23/535 ,  H01L21/768 ,  H01L29/06 ,  H01L29/66 ,  H01L29/417 ,  H01L29/78 ,  H01L27/088 ,  H01L21/8234

CPC classification number: H01L23/535 ,  H01L21/76895 ,  H01L21/823431 ,  H01L21/823475 ,  H01L21/823481 ,  H01L21/845 ,  H01L27/088 ,  H01L27/0886 ,  H01L27/1211 ,  H01L29/0649 ,  H01L29/41791 ,  H01L29/66545 ,  H01L29/785

Abstract: A semiconductor device and a method of manufacturing a semiconductor device, the device including gate structures on a substrate; source/drain layers on portions of the substrate that are adjacent the gate structures, respectively; first contact plugs contacting upper surfaces of the source/drain layers, respectively; a second contact plug contacting one of the gate structures, a sidewall of the second contact plug being covered by an insulating spacer; and a third contact plug commonly contacting an upper surface of at least one of the gate structures and at least one of the first contact plugs, at least a portion of a sidewall of the third contact plug not being covered by an insulating spacer.

公开(公告)号：US20210098377A1

公开(公告)日：2021-04-01

申请号：US17120616

申请日：2020-12-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyo-Jin KIM ,  Chang-Hwa KIM ,  Hwi-Chan JUN ,  Chul-Hong PARK ,  Jae-Seok YANG ,  Kwan-Young CHUN

IPC: H01L23/535 ,  H01L27/088 ,  H01L21/84 ,  H01L27/12 ,  H01L21/768 ,  H01L29/08 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/417 ,  H01L29/66 ,  H01L29/78

Abstract: A semiconductor device and a method of manufacturing a semiconductor device, the device including gate structures on a substrate; source/drain layers on portions of the substrate that are adjacent the gate structures, respectively; first contact plugs contacting upper surfaces of the source/drain layers, respectively; a second contact plug contacting one of the gate structures, a sidewall of the second contact plug being covered by an insulating spacer; and a third contact plug commonly contacting an upper surface of at least one of the gate structures and at least one of the first contact plugs, at least a portion of a sidewall of the third contact plug not being covered by an insulating spacer.

公开(公告)号：US20130248990A1

公开(公告)日：2013-09-26

申请号：US13718138

申请日：2012-12-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ho-Jun KIM ,  Hae-Wang LEE ,  Chul-Hong PARK ,  Dong-Kyun SOHN ,  Jong-Shik YOON

IPC: H01L23/538 ,  H01L29/78

CPC classification number: H01L23/5384 ,  H01L21/76816 ,  H01L21/76831 ,  H01L21/76834 ,  H01L21/76885 ,  H01L21/76897 ,  H01L21/823437 ,  H01L21/823475 ,  H01L23/5283 ,  H01L23/53238 ,  H01L23/53266 ,  H01L29/7827 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Semiconductor devices, and a method for fabricating the same, include an interlayer dielectric film pattern over a substrate, a first wiring within the interlayer dielectric film pattern and having a first length in a first direction, a second wiring within the interlayer dielectric film pattern and separated from the first wiring, and a spacer contacting the first wiring and the second wiring. The spacer electrically separates the first wiring and the second wiring from each other. The second wiring has a second length different from the first length in the first direction.

Abstract translation: 半导体器件及其制造方法包括在衬底上的层间电介质膜图案，层间电介质膜图案内的第一布线，并且具有第一方向的第一长度，层间电介质膜图案内的第二布线和 与第一布线分离，以及与第一布线和第二布线接触的间隔件。 间隔件将第一布线和第二布线彼此电分离。 第二布线具有与第一方向上的第一长度不同的第二长度。

公开(公告)号：US20170309569A1

公开(公告)日：2017-10-26

申请号：US15647467

申请日：2017-07-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Raheel Azmat ,  Sengupta RWIK ,  Su-Hyeon KIM ,  Chul-Hong PARK ,  Jae-Hyoung LIM

IPC: H01L23/528 ,  H01L29/66 ,  H01L29/165 ,  H01L29/161 ,  H01L29/16 ,  H01L29/06 ,  H01L21/285 ,  H01L27/092 ,  H01L21/8238 ,  H01L29/78 ,  H01L29/08

CPC classification number: H01L23/5286 ,  H01L21/28518 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823871 ,  H01L21/823878 ,  H01L27/0207 ,  H01L27/092 ,  H01L27/0924 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/7848

Abstract: A logic semiconductor device includes a plurality of active patterns extending in a horizontal direction and being spaced apart from each other in a vertical direction, an isolation layer defining the active patterns, a plurality of gate patterns extending in the vertical direction on the active patterns and the isolation layer, the gate patterns being spaced apart from each other in the horizontal direction, a plurality of lower wirings extending in the horizontal direction over the gate patterns, a plurality of upper wirings extending in the vertical direction over the lower wirings, a through contact connecting at least one upper wiring of the upper wirings and at least one gate pattern of the gate patterns, the through contact extending from a bottom surface of the upper wiring to a position under a bottom surface of one of the lower wirings relative to the active patterns.

公开(公告)号：US20190122988A1

公开(公告)日：2019-04-25

申请号：US16217220

申请日：2018-12-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyo-Jin KIM ,  Chang-Hwa KIM ,  Hwi-Chan JUN ,  Chul-Hong PARK ,  Jae-Seok YANG ,  Kwan-Young CHUN

IPC: H01L23/535 ,  H01L27/088 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/66 ,  H01L29/417 ,  H01L21/768 ,  H01L27/12 ,  H01L21/84 ,  H01L29/78

Abstract: A semiconductor device and a method of manufacturing a semiconductor device, the device including gate structures on a substrate; source/drain layers on portions of the substrate that are adjacent the gate structures, respectively; first contact plugs contacting upper surfaces of the source/drain layers, respectively; a second contact plug contacting one of the gate structures, a sidewall of the second contact plug being covered by an insulating spacer; and a third contact plug commonly contacting an upper surface of at least one of the gate structures and at least one of the first contact plugs, at least a portion of a sidewall of the third contact plug not being covered by an insulating spacer.

公开(公告)号：US20180157781A1

公开(公告)日：2018-06-07

申请号：US15701971

申请日：2017-09-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sidharth RASTOGI ,  Subhash KUCHANURI ,  Chul-Hong PARK ,  Jae-Seok YANG

IPC: G06F17/50 ,  H01L21/768 ,  H01L27/118 ,  H01L23/522

CPC classification number: G06F17/5072 ,  G06F17/5077 ,  H01L21/76838 ,  H01L23/5226 ,  H01L27/0207 ,  H01L27/11807 ,  H01L2027/11875

Abstract: A method of designing a layout of a semiconductor device includes designing layouts of cells, each layout including first conductive lines, the first conductive lines extending in a first direction and being spaced apart from each other in a second direction crossing the first direction, disposing the layouts of the cells to be adjacent to each other in the first direction, such that the first conductive lines in adjacent layouts of the cells are connected to each other, and disposing insulation blocks at a boundary area between adjacent ones of the layouts of the cells or in areas of the layouts of the cells adjacent to the boundary area, such that the insulation blocks block connections between some of the first conductive lines.

公开(公告)号：US20170117223A1

公开(公告)日：2017-04-27

申请号：US15188743

申请日：2016-06-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Raheel Azmat ,  Sengupta RWIK ,  Su-Hyeon KIM ,  Chul-Hong PARK ,  Jae-Hyoung LIM

IPC: H01L23/528 ,  H01L29/08 ,  H01L29/161 ,  H01L29/16 ,  H01L21/285 ,  H01L29/78 ,  H01L29/06 ,  H01L21/8238 ,  H01L29/66 ,  H01L27/092 ,  H01L29/165

CPC classification number: H01L23/5286 ,  H01L21/28518 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823871 ,  H01L21/823878 ,  H01L27/0207 ,  H01L27/092 ,  H01L27/0924 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/7848

Abstract: A logic semiconductor device includes a plurality of active patterns extending in a horizontal direction and being spaced apart from each other in a vertical direction, an isolation layer defining the active patterns, a plurality of gate patterns extending in the vertical direction on the active patterns and the isolation layer, the gate patterns being spaced apart from each other in the horizontal direction, a plurality of lower wirings extending in the horizontal direction over the gate patterns, a plurality of upper wirings extending in the vertical direction over the lower wirings, a through contact connecting at least one upper wiring of the upper wirings and at least one gate pattern of the gate patterns, the through contact extending from a bottom surface of the upper wiring to a position under a bottom surface of one of the lower wirings relative to the active patterns.