公开(公告)号：US20220108744A1

公开(公告)日：2022-04-07

申请号：US16952712

申请日：2020-11-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Lava Kumar Pulluru ,  Ankur Gupta ,  Parvinder Kumar Rana

IPC: G11C11/419

Abstract: A bitline precharge system is provided for a semiconductor memory device. The bitline precharge system comprises a voltage comparator circuit to output a reference voltage signal based on an input wordline voltage supply level (VDDWL), and a periphery power supply voltage (VDDP) level. A voltage control circuit is electrically coupled to a periphery power supply and the voltage comparator circuit to output a precharge voltage (VDDM) level based on the reference voltage signal and the periphery power supply voltage (VDDP) level. A bitline precharge circuit is electrically coupled to the voltage control circuit and a plurality of bitlines of the memory device to precharge the plurality of bitlines based on the precharge voltage (VDDM) level in response to a precharge enable signal during one of a read operation to read data from the memory device and a write operation to write data from the memory device. Further, the at least one bitline is discharged from the precharge voltage (VDDM) level during at least one of the read operation or the write operation.

公开(公告)号：US20210118494A1

公开(公告)日：2021-04-22

申请号：US16720888

申请日：2019-12-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ambuj JAIN ,  Akash Kumar Gupta ,  Manish Chandra Joshi ,  Parvinder Kumar Rana ,  Abhishek Kesarwani

IPC: G11C11/419

Abstract: Embodiments herein provide a Static Random-Access Memory (SRAM) system with a delay tuning circuitry and a delay control circuitry and a method thereof. Delay tuning circuitry in the SRAM system may provide a tuning of reset time in the generation of an internal clock by introducing a delay. The delay is introduced according to a process state of periphery circuitry in the SRAM. A delay control circuitry provides a control over delay in reset time of the internal clock by varying a discharge rate for each of a Dummy Bit Line (DBL) circuitry and Complementary Bit Line Circuitry (CDBL), by connecting a stack of NMOS transistors over discharge NMOS transistors.

公开(公告)号：US10147493B2

公开(公告)日：2018-12-04

申请号：US15665988

申请日：2017-08-01

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Parvinder Kumar Rana ,  Lava Kumar Pulluru ,  Manish Chandra Joshi

IPC: G11C16/32 ,  G11C16/08

Abstract: A system on-chip (SoC) device is provided. The SoC device includes an on-chip memory including memory banks, and internal clock generators. Each internal clock generator is coupled to one or more memory banks. Each internal clock generator generates one or more of an internal clock signal, a control signal and a clock reset signal locally for the memory bank to which the internal clock generator is coupled.

公开(公告)号：US20240347104A1

公开(公告)日：2024-10-17

申请号：US18378598

申请日：2023-10-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Lava Kumar Pulluru ,  Manish Chandra Joshi ,  Parvinder Kumar Rana ,  Poornima Venkatasubramanian ,  Ved Prakash ,  Chaitanya Vavilla

IPC: G11C11/419

CPC classification number: G11C11/419

Abstract: A memory device and its operation reduce the impact of a parasitic wire Resistance and Capacitance (RC) in the memory device. At least one of a rise transition and a fall transition of a signal transmitted by a long metal line is sensed by a sense circuit of a signal boosting circuit. At least one of a Pull Up (PU) circuit and a Pull Down (PD) circuit of the signal boosting circuit is enabled to speed-up one or both of the rise transition and the fall transition of the signal transmitted by the long metal line. The duration of an operation of one of the PU circuit and the PD circuit may be controlled using a control signal.

公开(公告)号：US10998018B1

公开(公告)日：2021-05-04

申请号：US16746378

申请日：2020-01-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Shubham Ranjan ,  Parvinder Kumar Rana ,  Janardhan Achanta ,  Manish Chandra Joshi

IPC: G11C7/12 ,  G11C7/10

Abstract: Provided are apparatus and methods for compensating fabrication process variation of on-chip component(s) in shared memory bank. The method includes tracking a flip voltage level and tracking a discharge leakage current to disconnect a keeper circuit from the local read bit-line. The method includes controlling a read current and the discharge leakage current based on determining at least one of fast transistor and slow transistor associated with the at least one the keeper circuit and a bit-cell.

公开(公告)号：US10672443B2

公开(公告)日：2020-06-02

申请号：US16166647

申请日：2018-10-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ankur Gupta ,  Abhishek Kesarwani ,  Parvinder Kumar Rana ,  Manish Chandra Joshi ,  Lava Kumar Pulluru

IPC: G11C8/10 ,  G11C7/22 ,  G11C8/06 ,  G11C8/08 ,  G11C17/12 ,  G11C11/418 ,  G11C11/417

Abstract: A fin-Field Effect Transistor based system on chip (SoC) memory is provided and includes a control block, first logic gates, and row decoder blocks. The control block includes a clock generator circuit that generates an internal clock signal, and a global driver circuit coupled to the clock generator circuit that drives a global clock signal. Each row decoder block includes a second logic gate that receives higher order non-clocked address signals via input terminals, a transmission gate that combines the global clock signal and the higher order non-clocked address signals, third logic gates that receive lower order non-clocked address signals and higher order clocked address signals, and output a combined lower order address and higher order address along with the global clock signal, level shifter circuits that receive the outputs, and word-line driver circuits that generate word-lines based on the output of the level shifter circuits.

公开(公告)号：US10665295B2

公开(公告)日：2020-05-26

申请号：US16191717

申请日：2018-11-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Lava Kumar Pulluru ,  Parvinder Kumar Rana ,  Akash Kumar Gupta ,  Gayatri Nair

IPC: G11C11/419 ,  G11C11/4097 ,  G11C7/10 ,  G11C7/12 ,  G11C7/18 ,  G11C8/12 ,  G11C11/418

Abstract: A static random-access memory (SRAM) system using a virtual banking architecture includes a processor communicatively coupled to an SRAM, and a plurality of circuits disposed in the SRAM and operated under control of the processor. The circuits include a divide circuit, a select circuit disposed in the divide circuit, and a local input/output circuit. The divide circuit divides a bank into first and second bit cell arrays, in which the first bit cell array and/or the second bit cell array includes at least one bit line. The select circuit is connected between the first and second bit cell arrays, and the select circuit selects one of the first and second bit cell arrays according to a predefined select logic. The local input/output circuit is connected to the select circuit and generates an output according to one or more predefined operations of the local input/output circuit.

公开(公告)号：US10566959B1

公开(公告)日：2020-02-18

申请号：US16276212

申请日：2019-02-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sajal Mittal ,  Parvinder Kumar Rana ,  Abhishek Ghosh ,  Rajeela Deshpande

IPC: H03K3/3562 ,  H03K3/356 ,  H03K3/037 ,  G06F1/10 ,  G06F1/12

Abstract: A method and a sense amplifier flip-flop (SAFF) for fixing setup time violations in an integrated circuit (IC) design. The SAFF includes a master latch coupled to a slave latch, wherein the master latch includes a sense amplifier and the SAFF is configured with an equal number of p-type metal oxide semiconductor (PMOS) transistors and n-type metal oxide semiconductor (NMOS) transistors to reduce block area of an integrated circuit (IC). The method includes receiving a clock signal, receiving a data signal, applying the data signal to the sense amplifier when the clock signal is at a low level, wherein a portion of the sense amplifier is responsive to the inverted clock signal, storing a value of the data signal in the slave latch when the clock signal transitions from the low level to the high level, and providing an output signal from the slave latch.

公开(公告)号：US20180083036A1

公开(公告)日：2018-03-22

申请号：US15613712

申请日：2017-06-05

Applicant: Samsung Electronics CO., Ltd.

Inventor： Shyam AGARWAL ,  Abhishek Ghosh ,  Parvinder Kumar Rana

IPC: H01L27/118

CPC classification number: H01L27/11807 ,  H01L2027/11831

Abstract: Inventive concepts describe a method for high performance standard cell design techniques in FinFET based library using LLE. Inventive concepts describe a fabrication process using a standard FinFET cell layout having double diffusion breaks (DDBs) and single diffusion breaks (SDBs). According to one example embodiment, the method comprises of removing one or more fingers of a P-type FinFet (PFET) from a standard FinFET cell layout. After removing the one or more fingers, a Half-Double Diffusion Break (Half-DDB) is introduced on a N-type FinFET (NFET) side inside a cell boundary using a cut-poly layer. The cut-poly layer not only isolates the PFET and NFET gates and also becomes an integral part of hybrid structure. Further, the removed one or more fingers of PFET gates are converted to two floating PFET gates by shorting a drain terminal and a source terminal of the PFET gate to a common power net.

公开(公告)号：US11790982B2

公开(公告)日：2023-10-17

申请号：US17443480

申请日：2021-07-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ankur Gupta ,  Manish Chandra Joshi ,  Parvinder Kumar Rana

IPC: G11C11/4093 ,  G11C11/408 ,  G11C5/14 ,  G11C5/06 ,  G11C11/4074

CPC classification number: G11C11/4093 ,  G11C5/06 ,  G11C5/14 ,  G11C11/4074 ,  G11C11/4085

Abstract: The present invention discloses a wordline driver circuit for a random-access memory (RAM), which can reduce leakage during power down mode. The circuit includes a pre-driver stage on header and footer. The pre-driver stage includes a strap buffer defining a header and comprising a first switch connecting a first set of wordlines to a first voltage. The pre-driver stage includes an input-output buffer defining a footer and comprising a second switch connecting a second set of wordlines to a second voltage. In the pre-driver stage, the strap buffer further includes a third switch connecting the second set of wordlines to the first voltage and a fourth switch connecting the first set of wordlines to the second voltage.