公开(公告)号：US10803929B2

公开(公告)日：2020-10-13

申请号：US16857269

申请日：2020-04-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Lava Kumar Pulluru ,  Parvinder Kumar Rana ,  Akash Kumar Gupta ,  Gayatri Nair

IPC: G11C11/419 ,  G11C11/4097 ,  G11C7/10 ,  G11C7/18 ,  G11C8/12 ,  G11C11/418 ,  G11C7/12

Abstract: A static random-access memory (SRAM) system using a virtual banking architecture includes a processor communicatively coupled to an SRAM, and a plurality of circuits disposed in the SRAM and operated under control of the processor. The circuits include a divide circuit, a select circuit disposed in the divide circuit, and a local input/output circuit. The divide circuit divides a bank into first and second bit cell arrays, in which the first bit cell array and/or the second bit cell array includes at least one bit line. The select circuit is connected between the first and second bit cell arrays, and the select circuit selects one of the first and second bit cell arrays according to a predefined select logic. The local input/output circuit is connected to the select circuit and generates an output according to one or more predefined operations of the local input/output circuit.

公开(公告)号：US10665295B2

公开(公告)日：2020-05-26

申请号：US16191717

申请日：2018-11-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Lava Kumar Pulluru ,  Parvinder Kumar Rana ,  Akash Kumar Gupta ,  Gayatri Nair

IPC: G11C11/419 ,  G11C11/4097 ,  G11C7/10 ,  G11C7/12 ,  G11C7/18 ,  G11C8/12 ,  G11C11/418

Abstract: A static random-access memory (SRAM) system using a virtual banking architecture includes a processor communicatively coupled to an SRAM, and a plurality of circuits disposed in the SRAM and operated under control of the processor. The circuits include a divide circuit, a select circuit disposed in the divide circuit, and a local input/output circuit. The divide circuit divides a bank into first and second bit cell arrays, in which the first bit cell array and/or the second bit cell array includes at least one bit line. The select circuit is connected between the first and second bit cell arrays, and the select circuit selects one of the first and second bit cell arrays according to a predefined select logic. The local input/output circuit is connected to the select circuit and generates an output according to one or more predefined operations of the local input/output circuit.

公开(公告)号：US20210118494A1

公开(公告)日：2021-04-22

申请号：US16720888

申请日：2019-12-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ambuj JAIN ,  Akash Kumar Gupta ,  Manish Chandra Joshi ,  Parvinder Kumar Rana ,  Abhishek Kesarwani

IPC: G11C11/419

Abstract: Embodiments herein provide a Static Random-Access Memory (SRAM) system with a delay tuning circuitry and a delay control circuitry and a method thereof. Delay tuning circuitry in the SRAM system may provide a tuning of reset time in the generation of an internal clock by introducing a delay. The delay is introduced according to a process state of periphery circuitry in the SRAM. A delay control circuitry provides a control over delay in reset time of the internal clock by varying a discharge rate for each of a Dummy Bit Line (DBL) circuitry and Complementary Bit Line Circuitry (CDBL), by connecting a stack of NMOS transistors over discharge NMOS transistors.

公开(公告)号：US11017848B2

公开(公告)日：2021-05-25

申请号：US16720888

申请日：2019-12-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ambuj Jain ,  Akash Kumar Gupta ,  Manish Chandra Joshi ,  Parvinder Kumar Rana ,  Abhishek Kesarwani

IPC: G11C7/08 ,  G11C11/419

Abstract: Embodiments herein provide a Static Random-Access Memory (SRAM) system with a delay tuning circuitry and a delay control circuitry and a method thereof. Delay tuning circuitry in the SRAM system may provide a tuning of reset time in the generation of an internal clock by introducing a delay. The delay is introduced according to a process state of periphery circuitry in the SRAM. A delay control circuitry provides a control over delay in reset time of the internal clock by varying a discharge rate for each of a Dummy Bit Line (DBL) circuitry and Complementary Bit Line Circuitry (CDBL), by connecting a stack of NMOS transistors over discharge NMOS transistors.

公开(公告)号：US10304507B2

公开(公告)日：2019-05-28

申请号：US15870013

申请日：2018-01-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Manish Chandra Joshi ,  Parvinder Kumar Rana ,  Akash Kumar Gupta

IPC: G11C8/00 ,  G11C7/18 ,  G11C5/06 ,  G11C7/02 ,  G11C8/14 ,  G11C7/22 ,  G11C7/10

Abstract: A memory for providing a signal buffering scheme for array and periphery signals and the operating method of the same are provided. The memory includes a plurality of columns of memory cells, a control circuit, and a control logic unit. The plurality of columns of memory cells may be connected to a local array signal generator via local control lines, which are connected to a global array signal generator via global control lines for receiving array signals. The control circuit may be connected to the memory cells for providing periphery signals. The control logic unit may be connected to the memory cells through a hierarchical structure of the global control lines and the local control lines. The control logic unit may be configured to provide the array signals and periphery signals having the same polarity to the global control lines and the local control lines.