公开(公告)号：US12087387B2

公开(公告)日：2024-09-10

申请号：US17750690

申请日：2022-05-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Lava Kumar Pulluru ,  Poornima Venkatasubramanian ,  Manish Chandra Joshi ,  Ved Prakash ,  Pushp Khatter

IPC: G11C7/10 ,  H03K3/037

CPC classification number: G11C7/1039 ,  G11C7/1066 ,  G11C7/1093 ,  H03K3/0372

Abstract: A memory device includes at least one bitcell; read circuitry coupled to the at least one bitcell; and screening circuitry coupled to the read circuitry, wherein the screening circuitry includes a master slave flip-flop configured to store an output of the at least one bitcell during a read operation of the memory device, wherein the master slave flip-flop includes a master latch and a slave latch; and a DOUT window controller coupled to the master slave flip-flop and configured to generate and control a master clock signal for the master latch to determine if the at least one bitcell is a weak bitcell; and generate and control a slave clock signal for the slave latch to enable toggling of the output of the at least one bitcell during a transparent window between the master clock signal and the slave clock signal.

公开(公告)号：US11790982B2

公开(公告)日：2023-10-17

申请号：US17443480

申请日：2021-07-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ankur Gupta ,  Manish Chandra Joshi ,  Parvinder Kumar Rana

IPC: G11C11/4093 ,  G11C11/408 ,  G11C5/14 ,  G11C5/06 ,  G11C11/4074

CPC classification number: G11C11/4093 ,  G11C5/06 ,  G11C5/14 ,  G11C11/4074 ,  G11C11/4085

Abstract: The present invention discloses a wordline driver circuit for a random-access memory (RAM), which can reduce leakage during power down mode. The circuit includes a pre-driver stage on header and footer. The pre-driver stage includes a strap buffer defining a header and comprising a first switch connecting a first set of wordlines to a first voltage. The pre-driver stage includes an input-output buffer defining a footer and comprising a second switch connecting a second set of wordlines to a second voltage. In the pre-driver stage, the strap buffer further includes a third switch connecting the second set of wordlines to the first voltage and a fourth switch connecting the first set of wordlines to the second voltage.

公开(公告)号：US12293806B2

公开(公告)日：2025-05-06

申请号：US18051142

申请日：2022-10-31

Applicant: Samsung Electronics Co., Ltd.

Inventor： Lava Kumar Pulluru ,  Gopi Sunanth Kumar Gogineni ,  Manish Chandra Joshi ,  Pushp Khatter

IPC: G11C7/10 ,  G11C7/12 ,  G11C7/22

Abstract: Various example embodiments of the inventive concepts include a SRAM apparatus including a left memory array and right memory array, each of the left memory array and the right memory array including a left memory array and a right memory array, each comprising a plurality of columns, the plurality of columns in each of the left memory array and the right memory array divided into a plurality of segments, and each of the segments comprising a plurality of memory bit cells, and central driver circuitry comprising a plurality of driver devices, each of the plurality of driver devices communicatively connected to a corresponding segment of the plurality of segments through a corresponding metal control line of a plurality of metal control lines, the central driver circuitry configured to route at least one array signal to at least one segment of the plurality of segments.

公开(公告)号：US11017848B2

公开(公告)日：2021-05-25

申请号：US16720888

申请日：2019-12-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ambuj Jain ,  Akash Kumar Gupta ,  Manish Chandra Joshi ,  Parvinder Kumar Rana ,  Abhishek Kesarwani

IPC: G11C7/08 ,  G11C11/419

Abstract: Embodiments herein provide a Static Random-Access Memory (SRAM) system with a delay tuning circuitry and a delay control circuitry and a method thereof. Delay tuning circuitry in the SRAM system may provide a tuning of reset time in the generation of an internal clock by introducing a delay. The delay is introduced according to a process state of periphery circuitry in the SRAM. A delay control circuitry provides a control over delay in reset time of the internal clock by varying a discharge rate for each of a Dummy Bit Line (DBL) circuitry and Complementary Bit Line Circuitry (CDBL), by connecting a stack of NMOS transistors over discharge NMOS transistors.

公开(公告)号：US10304507B2

公开(公告)日：2019-05-28

申请号：US15870013

申请日：2018-01-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Manish Chandra Joshi ,  Parvinder Kumar Rana ,  Akash Kumar Gupta

IPC: G11C8/00 ,  G11C7/18 ,  G11C5/06 ,  G11C7/02 ,  G11C8/14 ,  G11C7/22 ,  G11C7/10

Abstract: A memory for providing a signal buffering scheme for array and periphery signals and the operating method of the same are provided. The memory includes a plurality of columns of memory cells, a control circuit, and a control logic unit. The plurality of columns of memory cells may be connected to a local array signal generator via local control lines, which are connected to a global array signal generator via global control lines for receiving array signals. The control circuit may be connected to the memory cells for providing periphery signals. The control logic unit may be connected to the memory cells through a hierarchical structure of the global control lines and the local control lines. The control logic unit may be configured to provide the array signals and periphery signals having the same polarity to the global control lines and the local control lines.

公开(公告)号：US20240347104A1

公开(公告)日：2024-10-17

申请号：US18378598

申请日：2023-10-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Lava Kumar Pulluru ,  Manish Chandra Joshi ,  Parvinder Kumar Rana ,  Poornima Venkatasubramanian ,  Ved Prakash ,  Chaitanya Vavilla

IPC: G11C11/419

CPC classification number: G11C11/419

Abstract: A memory device and its operation reduce the impact of a parasitic wire Resistance and Capacitance (RC) in the memory device. At least one of a rise transition and a fall transition of a signal transmitted by a long metal line is sensed by a sense circuit of a signal boosting circuit. At least one of a Pull Up (PU) circuit and a Pull Down (PD) circuit of the signal boosting circuit is enabled to speed-up one or both of the rise transition and the fall transition of the signal transmitted by the long metal line. The duration of an operation of one of the PU circuit and the PD circuit may be controlled using a control signal.

公开(公告)号：US10998018B1

公开(公告)日：2021-05-04

申请号：US16746378

申请日：2020-01-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Shubham Ranjan ,  Parvinder Kumar Rana ,  Janardhan Achanta ,  Manish Chandra Joshi

IPC: G11C7/12 ,  G11C7/10

Abstract: Provided are apparatus and methods for compensating fabrication process variation of on-chip component(s) in shared memory bank. The method includes tracking a flip voltage level and tracking a discharge leakage current to disconnect a keeper circuit from the local read bit-line. The method includes controlling a read current and the discharge leakage current based on determining at least one of fast transistor and slow transistor associated with the at least one the keeper circuit and a bit-cell.

公开(公告)号：US10672443B2

公开(公告)日：2020-06-02

申请号：US16166647

申请日：2018-10-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ankur Gupta ,  Abhishek Kesarwani ,  Parvinder Kumar Rana ,  Manish Chandra Joshi ,  Lava Kumar Pulluru

IPC: G11C8/10 ,  G11C7/22 ,  G11C8/06 ,  G11C8/08 ,  G11C17/12 ,  G11C11/418 ,  G11C11/417

Abstract: A fin-Field Effect Transistor based system on chip (SoC) memory is provided and includes a control block, first logic gates, and row decoder blocks. The control block includes a clock generator circuit that generates an internal clock signal, and a global driver circuit coupled to the clock generator circuit that drives a global clock signal. Each row decoder block includes a second logic gate that receives higher order non-clocked address signals via input terminals, a transmission gate that combines the global clock signal and the higher order non-clocked address signals, third logic gates that receive lower order non-clocked address signals and higher order clocked address signals, and output a combined lower order address and higher order address along with the global clock signal, level shifter circuits that receive the outputs, and word-line driver circuits that generate word-lines based on the output of the level shifter circuits.

公开(公告)号：US12205636B2

公开(公告)日：2025-01-21

申请号：US18163584

申请日：2023-02-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Poornima Venkatasubramanian ,  Pushp Khatter ,  Lava Kumar Pulluru ,  Manish Chandra Joshi ,  Ved Prakash ,  Anurag Kumar ,  Surendra Deshmukh

IPC: G11C11/00 ,  G11C11/412 ,  G11C11/419

Abstract: A write assist circuit includes a first power control circuit and second power control circuit, each comprising a first switch and second switch. The first switch of first power control circuit has first drive strength and is configured to be controlled by a column select line, a power control line, a first bit line, and a power supply. The first switch of the second power control circuit has the first drive strength and is configured to be controlled by the column select line, the power control line, a second bit line, and the power supply. The second switch has a second drive strength and is configured to be controlled by the power control line. The first switches are configured to be controlled using input data on first- and second-bit line, respectively, for altering power supply to first inverter and second inverter of SRAM bitcell.

公开(公告)号：US20240321324A1

公开(公告)日：2024-09-26

申请号：US18375805

申请日：2023-10-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Poornima Venkatasubramanian ,  Gopi Sunanth Kumar Gogineni ,  Puneet Suri ,  Lava Kumar Pulluru ,  Karthikeyan Somashekara ,  Manish Chandra Joshi

IPC: G11C7/04 ,  G11C7/14 ,  G11C7/22

CPC classification number: G11C7/04 ,  G11C7/14 ,  G11C7/222

Abstract: A memory device, includes a voltage and temperature sensing circuit configured to generate a Pull Down (PD) signal that varies based on upon at least one of a voltage and temperature at the memory device; and primary pull down paths provided with secondary pull down paths, wherein the primary pull down paths are provided separately at a Dummy Read Bit line (DRBL) and a Dummy Global Read Bit line (DGRBL), wherein the secondary pull down paths are provided separately for the DRBL and the DGRBL parallel to the respective primary pull down paths. The voltage and temperature sensing circuit is configured to perform at least one of: controlling at least one of the secondary pull down paths based on a voltage of the PD signal; varying a discharge time of at least one of the dummy bit-lines based on the voltage of the PD signal; and generating an early reset signal at one of a high temperature condition and a high voltage condition based on the voltage of the PD signal.