公开(公告)号：US20210118494A1

公开(公告)日：2021-04-22

申请号：US16720888

申请日：2019-12-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ambuj JAIN ,  Akash Kumar Gupta ,  Manish Chandra Joshi ,  Parvinder Kumar Rana ,  Abhishek Kesarwani

IPC: G11C11/419

Abstract: Embodiments herein provide a Static Random-Access Memory (SRAM) system with a delay tuning circuitry and a delay control circuitry and a method thereof. Delay tuning circuitry in the SRAM system may provide a tuning of reset time in the generation of an internal clock by introducing a delay. The delay is introduced according to a process state of periphery circuitry in the SRAM. A delay control circuitry provides a control over delay in reset time of the internal clock by varying a discharge rate for each of a Dummy Bit Line (DBL) circuitry and Complementary Bit Line Circuitry (CDBL), by connecting a stack of NMOS transistors over discharge NMOS transistors.

公开(公告)号：US11017848B2

公开(公告)日：2021-05-25

申请号：US16720888

申请日：2019-12-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ambuj Jain ,  Akash Kumar Gupta ,  Manish Chandra Joshi ,  Parvinder Kumar Rana ,  Abhishek Kesarwani

IPC: G11C7/08 ,  G11C11/419

Abstract: Embodiments herein provide a Static Random-Access Memory (SRAM) system with a delay tuning circuitry and a delay control circuitry and a method thereof. Delay tuning circuitry in the SRAM system may provide a tuning of reset time in the generation of an internal clock by introducing a delay. The delay is introduced according to a process state of periphery circuitry in the SRAM. A delay control circuitry provides a control over delay in reset time of the internal clock by varying a discharge rate for each of a Dummy Bit Line (DBL) circuitry and Complementary Bit Line Circuitry (CDBL), by connecting a stack of NMOS transistors over discharge NMOS transistors.

公开(公告)号：US10672443B2

公开(公告)日：2020-06-02

申请号：US16166647

申请日：2018-10-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ankur Gupta ,  Abhishek Kesarwani ,  Parvinder Kumar Rana ,  Manish Chandra Joshi ,  Lava Kumar Pulluru

IPC: G11C8/10 ,  G11C7/22 ,  G11C8/06 ,  G11C8/08 ,  G11C17/12 ,  G11C11/418 ,  G11C11/417

Abstract: A fin-Field Effect Transistor based system on chip (SoC) memory is provided and includes a control block, first logic gates, and row decoder blocks. The control block includes a clock generator circuit that generates an internal clock signal, and a global driver circuit coupled to the clock generator circuit that drives a global clock signal. Each row decoder block includes a second logic gate that receives higher order non-clocked address signals via input terminals, a transmission gate that combines the global clock signal and the higher order non-clocked address signals, third logic gates that receive lower order non-clocked address signals and higher order clocked address signals, and output a combined lower order address and higher order address along with the global clock signal, level shifter circuits that receive the outputs, and word-line driver circuits that generate word-lines based on the output of the level shifter circuits.