公开(公告)号：US11776623B2

公开(公告)日：2023-10-03

申请号：US17815003

申请日：2022-07-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Lava Kumar Pulluru ,  Ankur Gupta ,  Parvinder Kumar Rana

IPC: G11C11/419

CPC classification number: G11C11/419

Abstract: A bitline precharge system is provided for a semiconductor memory device. The bitline precharge system comprises a voltage comparator circuit to output a reference voltage signal based on an input wordline voltage supply level (VDDWL), and a periphery power supply voltage (VDDP) level. A voltage control circuit is electrically coupled to a periphery power supply and the voltage comparator circuit to output a precharge voltage (VDDM) level based on the reference voltage signal and the periphery power supply voltage (VDDP) level. A bitline precharge circuit is electrically coupled to the voltage control circuit and a plurality of bitlines of the memory device to precharge the plurality of bitlines based on the precharge voltage (VDDM) level in response to a precharge enable signal during one of a read operation to read data from the memory device and a write operation to write data from the memory device. Further, the at least one bitline is discharged from the precharge voltage (VDDM) level during at least one of the read operation or the write operation.

公开(公告)号：US11017848B2

公开(公告)日：2021-05-25

申请号：US16720888

申请日：2019-12-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ambuj Jain ,  Akash Kumar Gupta ,  Manish Chandra Joshi ,  Parvinder Kumar Rana ,  Abhishek Kesarwani

IPC: G11C7/08 ,  G11C11/419

Abstract: Embodiments herein provide a Static Random-Access Memory (SRAM) system with a delay tuning circuitry and a delay control circuitry and a method thereof. Delay tuning circuitry in the SRAM system may provide a tuning of reset time in the generation of an internal clock by introducing a delay. The delay is introduced according to a process state of periphery circuitry in the SRAM. A delay control circuitry provides a control over delay in reset time of the internal clock by varying a discharge rate for each of a Dummy Bit Line (DBL) circuitry and Complementary Bit Line Circuitry (CDBL), by connecting a stack of NMOS transistors over discharge NMOS transistors.

公开(公告)号：US10304507B2

公开(公告)日：2019-05-28

申请号：US15870013

申请日：2018-01-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Manish Chandra Joshi ,  Parvinder Kumar Rana ,  Akash Kumar Gupta

IPC: G11C8/00 ,  G11C7/18 ,  G11C5/06 ,  G11C7/02 ,  G11C8/14 ,  G11C7/22 ,  G11C7/10

Abstract: A memory for providing a signal buffering scheme for array and periphery signals and the operating method of the same are provided. The memory includes a plurality of columns of memory cells, a control circuit, and a control logic unit. The plurality of columns of memory cells may be connected to a local array signal generator via local control lines, which are connected to a global array signal generator via global control lines for receiving array signals. The control circuit may be connected to the memory cells for providing periphery signals. The control logic unit may be connected to the memory cells through a hierarchical structure of the global control lines and the local control lines. The control logic unit may be configured to provide the array signals and periphery signals having the same polarity to the global control lines and the local control lines.

公开(公告)号：US11410720B2

公开(公告)日：2022-08-09

申请号：US16952712

申请日：2020-11-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Lava Kumar Pulluru ,  Ankur Gupta ,  Parvinder Kumar Rana

IPC: G11C11/419

Abstract: A bitline precharge system is provided for a semiconductor memory device. The bitline precharge system comprises a voltage comparator circuit to output a reference voltage signal based on an input wordline voltage supply level (VDDWL), and a periphery power supply voltage (VDDP) level. A voltage control circuit is electrically coupled to a periphery power supply and the voltage comparator circuit to output a precharge voltage (VDDM) level based on the reference voltage signal and the periphery power supply voltage (VDDP) level. A bitline precharge circuit is electrically coupled to the voltage control circuit and a plurality of bitlines of the memory device to precharge the plurality of bitlines based on the precharge voltage (VDDM) level in response to a precharge enable signal during one of a read operation to read data from the memory device and a write operation to write data from the memory device. Further, the at least one bitline is discharged from the precharge voltage (VDDM) level during at least one of the read operation or the write operation.

公开(公告)号：US11290092B1

公开(公告)日：2022-03-29

申请号：US17175818

申请日：2021-02-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ankur Gupta ,  Lava Kumar Pulluru ,  Parvinder Kumar Rana

IPC: G11C11/40 ,  H03K3/356 ,  H03K19/0185 ,  G11C11/419 ,  G11C11/412

Abstract: An apparatus includes a NMOS transistor having a drain, a first PMOS transistor having a drain connected to the drain of the NMOS transistor, a level shifter having an input and an output, the input of the level shifter being connected to the drain of the NMOS transistor and the drain of the first PMOS transistor, a first digital logic circuit having a drain and a gate, a first inverter having an input connected to the Aoutput of the level shifter and the drain of the first digital logic circuit, and a second digital logic circuit having an output connected to the gate of the first digital logic circuit, at least one condition being set in the apparatus during a read operation.

公开(公告)号：US10651850B2

公开(公告)日：2020-05-12

申请号：US16363292

申请日：2019-03-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sajal Mittal ,  Jaskaran Singh Bhatia ,  Rajeela Deshpande ,  Parvinder Kumar Rana ,  Nikhila C M ,  Abhishek Ghosh ,  Rahul Kataria

IPC: H03K19/00 ,  H03K19/0185 ,  H03K3/012 ,  H03K3/037

Abstract: A method and a flip-flop for designing low power integrated circuits (IC's). The method includes receiving at least one of a clock signal, a data signal, and a complimentary data signal. The complimentary data signal is produced by an input data inverter present in the flip-flop. Further, the method includes generating at least one master internal signal based on the received at least one of the clock signal, the data signal, and the complimentary data signal, when the clock signal is at a low logic level. Further, the method includes generating at least one slave internal signal based on at least one of the received clock signal and the generated at least one master internal signal, when the clock signal is at a high logic level. Further, the method includes generating an output signal based on the generated at least one slave internal signal.

公开(公告)号：US10522218B2

公开(公告)日：2019-12-31

申请号：US16190278

申请日：2018-11-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Parvinder Kumar Rana ,  Lava Kumar Pulluru ,  Shuvadeep Kumar ,  Ankur Gupta

IPC: G11C11/419 ,  G11C11/418

Abstract: Embodiments herein provide a method for reducing power dissipation in a Static Random Access Memory (SRAM) device. The method includes determining, by the tracking circuit, whether at least one SRAM Bit-Cell discharges power from at least one BL exceeding a pre-defined voltage level required for a sense amplifier to perform a read operation. Furthermore, the method includes reducing, by the WL driver, the power discharged from the at least one BL by controlling a WL voltage power supply switch of the WL driver using a SAE signal and adjusting a pulse width of the at least one WL to pull down the at least one WL using a NMOS circuit when the at least one SRAM Bit-Cell discharges the power from the at least one BL exceeding the pre-defined voltage level.

公开(公告)号：US20190006388A1

公开(公告)日：2019-01-03

申请号：US16124946

申请日：2018-09-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Shyam Agarwal ,  Abhishek Ghosh ,  Parvinder Kumar Rana

IPC: H01L27/118

Abstract: Inventive concepts describe a method for high performance standard cell design techniques in FinFET based library using LLE. Inventive concepts describe a fabrication process using a standard FinFET cell layout having double diffusion breaks (DDBs) and single diffusion breaks (SDBs). According to one example embodiment, the method comprises of removing one or more fingers of a P-type FinFet (PFET) from a standard FinFET cell layout. After removing the one or more fingers, a Half-Double Diffusion Break (Half-DDB) is introduced on a N-type FinFET (NFET) side inside a cell boundary using a cut-poly layer. The cut-poly layer not only isolates the PFET and NFET gates and also becomes an integral part of hybrid structure. Further, the removed one or more fingers of PFET gates are converted to two floating PFET gates by shorting a drain terminal and a source terminal of the PFET gate to a common power net.

公开(公告)号：US10103172B2

公开(公告)日：2018-10-16

申请号：US15613712

申请日：2017-06-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Shyam Agarwal ,  Abhishek Ghosh ,  Parvinder Kumar Rana

IPC: H01L21/84 ,  H01L27/118

Abstract: Inventive concepts describe a method for high performance standard cell design techniques in FinFET based library using LLE. Inventive concepts describe a fabrication process using a standard FinFET cell layout having double diffusion breaks (DDBs) and single diffusion breaks (SDBs). According to one example embodiment, the method comprises of removing one or more fingers of a P-type FinFet (PFET) from a standard FinFET cell layout. After removing the one or more fingers, a Half-Double Diffusion Break (Half-DDB) is introduced on a N-type FinFET (NFET) side inside a cell boundary using a cut-poly layer. The cut-poly layer not only isolates the PFET and NFET gates and also becomes an integral part of hybrid structure. Further, the removed one or more fingers of PFET gates are converted to two floating PFET gates by shorting a drain terminal and a source terminal of the PFET gate to a common power net.

公开(公告)号：US20220366970A1

公开(公告)日：2022-11-17

申请号：US17815003

申请日：2022-07-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Lava Kumar Pulluru ,  Ankur Gupta ,  Parvinder Kumar Rana

IPC: G11C11/419

Abstract: A bitline precharge system is provided for a semiconductor memory device. The bitline precharge system comprises a voltage comparator circuit to output a reference voltage signal based on an input wordline voltage supply level (VDDWL), and a periphery power supply voltage (VDDP) level. A voltage control circuit is electrically coupled to a periphery power supply and the voltage comparator circuit to output a precharge voltage (VDDM) level based on the reference voltage signal and the periphery power supply voltage (VDDP) level. A bitline precharge circuit is electrically coupled to the voltage control circuit and a plurality of bitlines of the memory device to precharge the plurality of bitlines based on the precharge voltage (VDDM) level in response to a precharge enable signal during one of a read operation to read data from the memory device and a write operation to write data from the memory device. Further, the at least one bitline is discharged from the precharge voltage (VDDM) level during at least one of the read operation or the write operation.