公开(公告)号：US11152942B2

公开(公告)日：2021-10-19

申请号：US16807640

申请日：2020-03-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hareharan Nagarajan ,  Abhishek Ghosh ,  Sajal Mittal

IPC: H03K19/21 ,  H03K19/0948

Abstract: A CMOS transistor circuit including: a first block generating a first output signal of a NOR state, in response to first and second input signals; a second block including a first AND-OR gate, the second block generating a second output signal of an OR or an AND state, the second block receiving the first and second input signals and the first output signal; a third block generating a third output signal of the NOR state, in response to a third input signal and the second output signal; a fourth block including a second AND-OR gate, the fourth block generating a fourth output signal of the OR or the AND state in response to the third input signal, the second output signal and the third output signal; and a fifth block including an inverter gate, the fifth block generating a fifth output signal in response to the fourth output signal.

公开(公告)号：US20210173006A1

公开(公告)日：2021-06-10

申请号：US17117544

申请日：2020-12-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Arani Roy ,  Arava Prakash ,  Aroma Bhat ,  Mitesh Goyal ,  Abhishek Ghosh

IPC: G01R31/3177 ,  H03K3/037 ,  G01R31/317

Abstract: A True Single Phase Clock (TSPC) pre-charge based flip-flop is provided. The flip-flop includes a scan section, a master section, and a slave section. The scan section receives a scan enable signal, a scan input signal, a clock signal, and feedback data from the master section, and outputs an internal signal to the master section based on the scan enable signal, the scan input signal, the clock signal, and the feedback data. The master section is coupled to the scan section and receives the internal signal and a data input, and outputs a master feedback signal to the slave section based on the internal signal, the data input, and the feedback data. The slave section is coupled to the master section and generates an output by latching the master feedback signal received from the master section according to the clock signal. The clock signal is a True-Single-Phase-Clock (TSPC).

公开(公告)号：US11271011B2

公开(公告)日：2022-03-08

申请号：US16924377

申请日：2020-07-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Shyam Agarwal ,  Abhishek Ghosh ,  Parvinder Kumar Rana

IPC: H01L27/118 ,  H01L21/8238 ,  H01L27/02 ,  H01L27/092

Abstract: Inventive concepts describe a method for high performance standard cell design techniques in FinFET based library using LLE. Inventive concepts describe a fabrication process using a standard FinFET cell layout having double diffusion breaks (DDBs) and single diffusion breaks (SDBs). According to one example embodiment, the method comprises of removing one or more fingers of a P-type FinFet (PFET) from a standard FinFET cell layout. After removing the one or more fingers, a Half-Double Diffusion Break (Half-DDB) is introduced on a N-type FinFET (NFET) side inside a cell boundary using a cut-poly layer. The cut-poly layer not only isolates the PFET and NFET gates and also becomes an integral part of hybrid structure. Further, the removed one or more fingers of PFET gates are converted to two floating PFET gates by shorting a drain terminal and a source terminal of the PFET gate to a common power net.

公开(公告)号：US10748932B2

公开(公告)日：2020-08-18

申请号：US16124946

申请日：2018-09-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Shyam Agarwal ,  Abhishek Ghosh ,  Parvinder Kumar Rana

IPC: H01L27/118 ,  H01L21/8238 ,  H01L27/02 ,  H01L27/092

Abstract: Inventive concepts describe a method for high performance standard cell design techniques in FinFET based library using LLE. Inventive concepts describe a fabrication process using a standard FinFET cell layout having double diffusion breaks (DDBs) and single diffusion breaks (SDBs). According to one example embodiment, the method comprises of removing one or more fingers of a P-type FinFet (PFET) from a standard FinFET cell layout. After removing the one or more fingers, a Half-Double Diffusion Break (Half-DDB) is introduced on a N-type FinFET (NFET) side inside a cell boundary using a cut-poly layer. The cut-poly layer not only isolates the PFET and NFET gates and also becomes an integral part of hybrid structure. Further, the removed one or more fingers of PFET gates are converted to two floating PFET gates by shorting a drain terminal and a source terminal of the PFET gate to a common power net.

公开(公告)号：US20200067507A1

公开(公告)日：2020-02-27

申请号：US16363292

申请日：2019-03-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sajal Mittal ,  Jaskaran Singh Bhatia ,  Rajeela Deshpande ,  Parvinder Kumar Rana ,  Nikhila C M ,  Abhishek Ghosh ,  Rahul Kataria

IPC: H03K19/00 ,  H03K3/037 ,  H03K3/012 ,  H03K19/0185

Abstract: A method and a flip-flop for designing low power integrated circuits (IC's). The method includes receiving at least one of a clock signal, a data signal, and a complimentary data signal. The complimentary data signal is produced by an input data inverter present in the flip-flop. Further, the method includes generating at least one master internal signal based on the received at least one of the clock signal, the data signal, and the complimentary data signal, when the clock signal is at a low logic level. Further, the method includes generating at least one slave internal signal based on at least one of the received clock signal and the generated at least one master internal signal, when the clock signal is at a high logic level. Further, the method includes generating an output signal based on the generated at least one slave internal signal.

公开(公告)号：US10812055B2

公开(公告)日：2020-10-20

申请号：US16661205

申请日：2019-10-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sajal Mittal ,  Aroma Bhat ,  Hareharan Nagarajan ,  Rahul Kataria ,  Abhishek Ghosh

IPC: H03K3/356 ,  H03K3/037

Abstract: Embodiments herein disclose a flip flop comprising at least one of a slave circuit and a retention circuit receiving an input from a master circuit. The output circuit receives an input (X1) from at least one of the slave circuit and the retention circuit. A first node and a second node in the retention circuit receive a power supply from a global power supply through transistors, when a retention is 0 in the retention circuit, so that the slave circuit retains a current state of the X1 and X2 irrespective of a clock input in the slave circuit, and the output circuit receives the stored state of the retention circuit, when a local power supply is turned ON.

公开(公告)号：US20220173725A1

公开(公告)日：2022-06-02

申请号：US17188510

申请日：2021-03-01

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： AROMA BHAT ,  Arani Roy ,  Mitesh Goyal ,  Abhishek Ghosh

IPC: H03K3/037

Abstract: A True Single-Phase Clock (TSPC) NAND-based reset flip-flop includes a reset functionality to perform a reset operation. The flip-flop with the reset functionality includes a master section and a slave section. The reset functionality is achieved using two transistors in the master section. The master section and the slave section operate using the TSPC. The master section and the slave section may include a plurality of NAND circuits and a NAND and NOR circuit for performing the reset operation. The master section outputs a plurality of internal signals on receiving a data input, a scan enable signal, a scan input signal, a reset control signal, and a clock signal. The slave section generates an output on receiving the plurality of internal signals received from the master section.

公开(公告)号：US20210184660A1

公开(公告)日：2021-06-17

申请号：US17118082

申请日：2020-12-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Aroma Bhat ,  Abdur Rakheeb ,  Arani Roy ,  Mitesh Goyal ,  Abhishek Ghosh

IPC: H03K3/3562 ,  G01R31/3177

Abstract: A pre-discharging based flip-flop having a negative setup time can include a flip-flop with an inverted output QN. The flip-flop includes a master section and a slave section. The master section latches a data input or a scan input signal based on a scan enable signal, and the slave section retains a previous value of the inverted output QN when a clock signal is at a low logic level. The master section retains a previously latched value of the data input or the scan input signal and the slave section fetches the latched value of the master section and provides a new inverted output QN when the clock signal is at a high logic level. Further, the master section includes sub-sections that are operated using a negative clock signal. An output of the master section is discharged to zero for a half of a phase of the clock cycle.

公开(公告)号：US10566959B1

公开(公告)日：2020-02-18

申请号：US16276212

申请日：2019-02-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sajal Mittal ,  Parvinder Kumar Rana ,  Abhishek Ghosh ,  Rajeela Deshpande

IPC: H03K3/3562 ,  H03K3/356 ,  H03K3/037 ,  G06F1/10 ,  G06F1/12

Abstract: A method and a sense amplifier flip-flop (SAFF) for fixing setup time violations in an integrated circuit (IC) design. The SAFF includes a master latch coupled to a slave latch, wherein the master latch includes a sense amplifier and the SAFF is configured with an equal number of p-type metal oxide semiconductor (PMOS) transistors and n-type metal oxide semiconductor (NMOS) transistors to reduce block area of an integrated circuit (IC). The method includes receiving a clock signal, receiving a data signal, applying the data signal to the sense amplifier when the clock signal is at a low level, wherein a portion of the sense amplifier is responsive to the inverted clock signal, storing a value of the data signal in the slave latch when the clock signal transitions from the low level to the high level, and providing an output signal from the slave latch.

公开(公告)号：US20180083036A1

公开(公告)日：2018-03-22

申请号：US15613712

申请日：2017-06-05

Applicant: Samsung Electronics CO., Ltd.

Inventor： Shyam AGARWAL ,  Abhishek Ghosh ,  Parvinder Kumar Rana

IPC: H01L27/118

CPC classification number: H01L27/11807 ,  H01L2027/11831

Abstract: Inventive concepts describe a method for high performance standard cell design techniques in FinFET based library using LLE. Inventive concepts describe a fabrication process using a standard FinFET cell layout having double diffusion breaks (DDBs) and single diffusion breaks (SDBs). According to one example embodiment, the method comprises of removing one or more fingers of a P-type FinFet (PFET) from a standard FinFET cell layout. After removing the one or more fingers, a Half-Double Diffusion Break (Half-DDB) is introduced on a N-type FinFET (NFET) side inside a cell boundary using a cut-poly layer. The cut-poly layer not only isolates the PFET and NFET gates and also becomes an integral part of hybrid structure. Further, the removed one or more fingers of PFET gates are converted to two floating PFET gates by shorting a drain terminal and a source terminal of the PFET gate to a common power net.