公开(公告)号：US11152942B2

公开(公告)日：2021-10-19

申请号：US16807640

申请日：2020-03-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hareharan Nagarajan ,  Abhishek Ghosh ,  Sajal Mittal

IPC: H03K19/21 ,  H03K19/0948

Abstract: A CMOS transistor circuit including: a first block generating a first output signal of a NOR state, in response to first and second input signals; a second block including a first AND-OR gate, the second block generating a second output signal of an OR or an AND state, the second block receiving the first and second input signals and the first output signal; a third block generating a third output signal of the NOR state, in response to a third input signal and the second output signal; a fourth block including a second AND-OR gate, the fourth block generating a fourth output signal of the OR or the AND state in response to the third input signal, the second output signal and the third output signal; and a fifth block including an inverter gate, the fifth block generating a fifth output signal in response to the fourth output signal.

公开(公告)号：US20210167781A1

公开(公告)日：2021-06-03

申请号：US16807640

申请日：2020-03-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hareharan Nagarajan ,  Abhishek Ghosh ,  Sajal Mittal

IPC: H03K19/21 ,  H03K19/0948

Abstract: A CMOS transistor circuit including: a first block generating a first output signal of a NOR state, in response to first and second input signals; a second block including a first AND-OR gate, the second block generating a second output signal of an OR or an AND state, the second block receiving the first and second input signals and the first output signal; a third block generating a third output signal of the NOR state, in response to a third input signal and the second output signal; a fourth block including a second AND-OR gate, the fourth block generating a fourth output signal of the OR or the AND state in response to the third input signal, the second output signal and the third output signal; and a fifth block including an inverter gate, the fifth block generating a fifth output signal in response to the fourth output signal.

公开(公告)号：US20200136594A1

公开(公告)日：2020-04-30

申请号：US16661205

申请日：2019-10-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sajal Mittal ,  Aroma Bhat ,  Hareharan Nagarajan ,  Rahul Kataria ,  Abhishek Ghosh

IPC: H03K3/037

Abstract: Embodiments herein disclose a flip flop comprising at least one of a slave circuit and a retention circuit receiving an input from a master circuit. The output circuit receives an input (X1) from at least one of the slave circuit and the retention circuit. A first node and a second node in the retention circuit receive a power supply from a global power supply through transistors, when a retention is 0 in the retention circuit, so that the slave circuit retains a current state of the X1 and X2 irrespective of a clock input in the slave circuit, and the output circuit receives the stored state of the retention circuit, when a local power supply is turned ON.

公开(公告)号：US11050424B1

公开(公告)日：2021-06-29

申请号：US16894201

申请日：2020-06-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hareharan Nagarajan ,  Sajal Mittal ,  Abdur Rakheeb ,  Nandish Uppal Raravi ,  Vinod Sharma

IPC: H03K19/0185 ,  H03K3/012 ,  H03K3/037

Abstract: Methods and apparatus for implementing a current-mirror based level shifter circuit are provided. The current-mirror based level shifter circuit includes a current-mirror circuit, a feedback control circuit, a power down circuit and a plurality of inverter circuits. The apparatus is configured to provide a wide voltage shifting range using the current-mirror based level shifter circuit. The apparatus comprising a feedback loop with two diode connected transistors may provide a constant drivability to the node that drives the output, when a current-mirror circuit is turned-off.

公开(公告)号：US10812055B2

公开(公告)日：2020-10-20

申请号：US16661205

申请日：2019-10-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sajal Mittal ,  Aroma Bhat ,  Hareharan Nagarajan ,  Rahul Kataria ,  Abhishek Ghosh

IPC: H03K3/356 ,  H03K3/037

Abstract: Embodiments herein disclose a flip flop comprising at least one of a slave circuit and a retention circuit receiving an input from a master circuit. The output circuit receives an input (X1) from at least one of the slave circuit and the retention circuit. A first node and a second node in the retention circuit receive a power supply from a global power supply through transistors, when a retention is 0 in the retention circuit, so that the slave circuit retains a current state of the X1 and X2 irrespective of a clock input in the slave circuit, and the output circuit receives the stored state of the retention circuit, when a local power supply is turned ON.