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    Three-input exclusive NOR/OR gate using a CMOS circuit
    1.
    发明授权
    Three-input exclusive NOR/OR gate using a CMOS circuit 有权

    公开(公告)号：US11152942B2

    公开(公告)日：2021-10-19

    申请号：US16807640

    申请日：2020-03-03

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Hareharan Nagarajan ,  Abhishek Ghosh ,  Sajal Mittal

    IPC: H03K19/21 ,  H03K19/0948

    Abstract: A CMOS transistor circuit including: a first block generating a first output signal of a NOR state, in response to first and second input signals; a second block including a first AND-OR gate, the second block generating a second output signal of an OR or an AND state, the second block receiving the first and second input signals and the first output signal; a third block generating a third output signal of the NOR state, in response to a third input signal and the second output signal; a fourth block including a second AND-OR gate, the fourth block generating a fourth output signal of the OR or the AND state in response to the third input signal, the second output signal and the third output signal; and a fifth block including an inverter gate, the fifth block generating a fifth output signal in response to the fourth output signal.

    Sense amplifier flip-flop and method for fixing setup time violations in an integrated circuit
    2.
    发明授权
    Sense amplifier flip-flop and method for fixing setup time violations in an integrated circuit 有权

    公开(公告)号：US10566959B1

    公开(公告)日：2020-02-18

    申请号：US16276212

    申请日：2019-02-14

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Sajal Mittal ,  Parvinder Kumar Rana ,  Abhishek Ghosh ,  Rajeela Deshpande

    IPC: H03K3/3562 ,  H03K3/356 ,  H03K3/037 ,  G06F1/10 ,  G06F1/12

    Abstract: A method and a sense amplifier flip-flop (SAFF) for fixing setup time violations in an integrated circuit (IC) design. The SAFF includes a master latch coupled to a slave latch, wherein the master latch includes a sense amplifier and the SAFF is configured with an equal number of p-type metal oxide semiconductor (PMOS) transistors and n-type metal oxide semiconductor (NMOS) transistors to reduce block area of an integrated circuit (IC). The method includes receiving a clock signal, receiving a data signal, applying the data signal to the sense amplifier when the clock signal is at a low level, wherein a portion of the sense amplifier is responsive to the inverted clock signal, storing a value of the data signal in the slave latch when the clock signal transitions from the low level to the high level, and providing an output signal from the slave latch.

    Flip flop circuit
    5.
    发明授权
    Flip flop circuit 有权

    公开(公告)号：US10812055B2

    公开(公告)日：2020-10-20

    申请号：US16661205

    申请日：2019-10-23

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Sajal Mittal ,  Aroma Bhat ,  Hareharan Nagarajan ,  Rahul Kataria ,  Abhishek Ghosh

    IPC: H03K3/356 ,  H03K3/037

    Abstract: Embodiments herein disclose a flip flop comprising at least one of a slave circuit and a retention circuit receiving an input from a master circuit. The output circuit receives an input (X1) from at least one of the slave circuit and the retention circuit. A first node and a second node in the retention circuit receive a power supply from a global power supply through transistors, when a retention is 0 in the retention circuit, so that the slave circuit retains a current state of the X1 and X2 irrespective of a clock input in the slave circuit, and the output circuit receives the stored state of the retention circuit, when a local power supply is turned ON.

    THREE-INPUT EXCLUSIVE NOR/OR GATE USING A CMOS CIRCUIT
    6.
    发明申请
    THREE-INPUT EXCLUSIVE NOR/OR GATE USING A CMOS CIRCUIT 有权

    公开(公告)号：US20210167781A1

    公开(公告)日：2021-06-03

    申请号：US16807640

    申请日：2020-03-03

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Hareharan Nagarajan ,  Abhishek Ghosh ,  Sajal Mittal

    IPC: H03K19/21 ,  H03K19/0948

    Abstract: A CMOS transistor circuit including: a first block generating a first output signal of a NOR state, in response to first and second input signals; a second block including a first AND-OR gate, the second block generating a second output signal of an OR or an AND state, the second block receiving the first and second input signals and the first output signal; a third block generating a third output signal of the NOR state, in response to a third input signal and the second output signal; a fourth block including a second AND-OR gate, the fourth block generating a fourth output signal of the OR or the AND state in response to the third input signal, the second output signal and the third output signal; and a fifth block including an inverter gate, the fifth block generating a fifth output signal in response to the fourth output signal.

    Area and power efficient circuits for high-density standard cell libraries
    7.
    发明授权
    Area and power efficient circuits for high-density standard cell libraries 审中-公开

    公开(公告)号：US10672756B2

    公开(公告)日：2020-06-02

    申请号：US16238009

    申请日：2019-01-02

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Sajal Mittal ,  Abhishek Ghosh ,  Utkarsh Garg

    IPC: G06F7/50 ,  H01L27/02 ,  H03K19/0185 ,  G06F30/392 ,  H01L27/118

    Abstract: Example embodiments provides a full adder integrated circuit (ADDF) for improving area and power of an integrated circuit (IC). The method includes receiving three input signals and generating three corresponding complementary output signals. Further, the method includes generating an internal signal using two complementary output signals out of the generated three corresponding complementary output signals, and one of the three input signals. Further, the method includes generating an output summation signal using a complementary output signal out of the generated three corresponding complementary output signals, the generated internal signal and a complementary internal signal of the generated internal signal. Further, the method includes generating a carry-out signal using two complementary output signal out of the generated three corresponding complementary output signals, the generated internal signal and the complementary internal signal. Example embodiments herein also provide a four input multiplexer Integrated circuit (MXT4) for reducing the area of the IC.

    FLIP FLOP
    9.
    发明申请
    FLIP FLOP 审中-公开

    公开(公告)号：US20200136594A1

    公开(公告)日：2020-04-30

    申请号：US16661205

    申请日：2019-10-23

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Sajal Mittal ,  Aroma Bhat ,  Hareharan Nagarajan ,  Rahul Kataria ,  Abhishek Ghosh

    IPC: H03K3/037

    Abstract: Embodiments herein disclose a flip flop comprising at least one of a slave circuit and a retention circuit receiving an input from a master circuit. The output circuit receives an input (X1) from at least one of the slave circuit and the retention circuit. A first node and a second node in the retention circuit receive a power supply from a global power supply through transistors, when a retention is 0 in the retention circuit, so that the slave circuit retains a current state of the X1 and X2 irrespective of a clock input in the slave circuit, and the output circuit receives the stored state of the retention circuit, when a local power supply is turned ON.

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