公开(公告)号：US20230418556A1

公开(公告)日：2023-12-28

申请号：US17821763

申请日：2022-08-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Debojyoti Banerjee ,  Abhishek Ghosh ,  Raghavendra Ramakant Shirodkar ,  Rakesh Dimri ,  Utkarsh Garg

IPC: G06F7/501 ,  H03K19/20 ,  H03K17/687

CPC classification number: G06F7/501 ,  H03K19/20 ,  H03K17/6872

Abstract: Provided is an apparatus that includes an integrated circuit including a static complementary metal-oxide-semiconductor based full adder circuit. The integrated circuit includes a carry generation circuit configured to receive a first input and a second input to generate a carry, and a carry propagation circuit configured to receive the first input, the second input, and a third input to generate a propagated output. The integrated circuit further includes a carry output generation circuit configured to receive the generated carry and the propagated output to generate a final carry as an output, and a sum generation circuit configured to generate a sum output. The sum generation circuit includes the carry generation circuit and is configured to receive the first input, the second input, and generated carry to generate an exclusive NOR output, and further uses the generated exclusive NOR output and the third input to generate the sum output.

公开(公告)号：US10672756B2

公开(公告)日：2020-06-02

申请号：US16238009

申请日：2019-01-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sajal Mittal ,  Abhishek Ghosh ,  Utkarsh Garg

IPC: G06F7/50 ,  H01L27/02 ,  H03K19/0185 ,  G06F30/392 ,  H01L27/118

Abstract: Example embodiments provides a full adder integrated circuit (ADDF) for improving area and power of an integrated circuit (IC). The method includes receiving three input signals and generating three corresponding complementary output signals. Further, the method includes generating an internal signal using two complementary output signals out of the generated three corresponding complementary output signals, and one of the three input signals. Further, the method includes generating an output summation signal using a complementary output signal out of the generated three corresponding complementary output signals, the generated internal signal and a complementary internal signal of the generated internal signal. Further, the method includes generating a carry-out signal using two complementary output signal out of the generated three corresponding complementary output signals, the generated internal signal and the complementary internal signal. Example embodiments herein also provide a four input multiplexer Integrated circuit (MXT4) for reducing the area of the IC.