公开(公告)号：US20200067507A1

公开(公告)日：2020-02-27

申请号：US16363292

申请日：2019-03-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sajal Mittal ,  Jaskaran Singh Bhatia ,  Rajeela Deshpande ,  Parvinder Kumar Rana ,  Nikhila C M ,  Abhishek Ghosh ,  Rahul Kataria

IPC: H03K19/00 ,  H03K3/037 ,  H03K3/012 ,  H03K19/0185

Abstract: A method and a flip-flop for designing low power integrated circuits (IC's). The method includes receiving at least one of a clock signal, a data signal, and a complimentary data signal. The complimentary data signal is produced by an input data inverter present in the flip-flop. Further, the method includes generating at least one master internal signal based on the received at least one of the clock signal, the data signal, and the complimentary data signal, when the clock signal is at a low logic level. Further, the method includes generating at least one slave internal signal based on at least one of the received clock signal and the generated at least one master internal signal, when the clock signal is at a high logic level. Further, the method includes generating an output signal based on the generated at least one slave internal signal.

公开(公告)号：US10651850B2

公开(公告)日：2020-05-12

申请号：US16363292

申请日：2019-03-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sajal Mittal ,  Jaskaran Singh Bhatia ,  Rajeela Deshpande ,  Parvinder Kumar Rana ,  Nikhila C M ,  Abhishek Ghosh ,  Rahul Kataria

IPC: H03K19/00 ,  H03K19/0185 ,  H03K3/012 ,  H03K3/037

Abstract: A method and a flip-flop for designing low power integrated circuits (IC's). The method includes receiving at least one of a clock signal, a data signal, and a complimentary data signal. The complimentary data signal is produced by an input data inverter present in the flip-flop. Further, the method includes generating at least one master internal signal based on the received at least one of the clock signal, the data signal, and the complimentary data signal, when the clock signal is at a low logic level. Further, the method includes generating at least one slave internal signal based on at least one of the received clock signal and the generated at least one master internal signal, when the clock signal is at a high logic level. Further, the method includes generating an output signal based on the generated at least one slave internal signal.

公开(公告)号：US10566959B1

公开(公告)日：2020-02-18

申请号：US16276212

申请日：2019-02-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sajal Mittal ,  Parvinder Kumar Rana ,  Abhishek Ghosh ,  Rajeela Deshpande

IPC: H03K3/3562 ,  H03K3/356 ,  H03K3/037 ,  G06F1/10 ,  G06F1/12

Abstract: A method and a sense amplifier flip-flop (SAFF) for fixing setup time violations in an integrated circuit (IC) design. The SAFF includes a master latch coupled to a slave latch, wherein the master latch includes a sense amplifier and the SAFF is configured with an equal number of p-type metal oxide semiconductor (PMOS) transistors and n-type metal oxide semiconductor (NMOS) transistors to reduce block area of an integrated circuit (IC). The method includes receiving a clock signal, receiving a data signal, applying the data signal to the sense amplifier when the clock signal is at a low level, wherein a portion of the sense amplifier is responsive to the inverted clock signal, storing a value of the data signal in the slave latch when the clock signal transitions from the low level to the high level, and providing an output signal from the slave latch.