公开(公告)号：US20190058461A1

公开(公告)日：2019-02-21

申请号：US16101789

申请日：2018-08-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Shyam AGARWAL ,  Sandeep B V ,  Shreyas Samraksh Jayaprakash ,  Abhishek Kumar Ghosh ,  Parvinder Kumar Rana

IPC: H03K3/3562 ,  H01L27/11 ,  H03K3/012 ,  H03K19/017 ,  G11C11/41

Abstract: Various example embodiments herein disclose a flip-flop including a master latch comprising one of: a plurality of P-type metal-oxide-semiconductor (PMOS) and a plurality of N-type metal-oxide-semiconductor (NMOS). A slave latch includes one of: a plurality of PMOS and a plurality of NMOS. An inverted clock signal input is communicatively connected with the master latch and the slave latch. The master latch includes a single pre-charge node. The single pre-charge node sets up a data capture path in the flip flop. Data is stored in the master latch and the slave latch via the pre-charge node.

公开(公告)号：US20180083036A1

公开(公告)日：2018-03-22

申请号：US15613712

申请日：2017-06-05

Applicant: Samsung Electronics CO., Ltd.

Inventor： Shyam AGARWAL ,  Abhishek Ghosh ,  Parvinder Kumar Rana

IPC: H01L27/118

CPC classification number: H01L27/11807 ,  H01L2027/11831

Abstract: Inventive concepts describe a method for high performance standard cell design techniques in FinFET based library using LLE. Inventive concepts describe a fabrication process using a standard FinFET cell layout having double diffusion breaks (DDBs) and single diffusion breaks (SDBs). According to one example embodiment, the method comprises of removing one or more fingers of a P-type FinFet (PFET) from a standard FinFET cell layout. After removing the one or more fingers, a Half-Double Diffusion Break (Half-DDB) is introduced on a N-type FinFET (NFET) side inside a cell boundary using a cut-poly layer. The cut-poly layer not only isolates the PFET and NFET gates and also becomes an integral part of hybrid structure. Further, the removed one or more fingers of PFET gates are converted to two floating PFET gates by shorting a drain terminal and a source terminal of the PFET gate to a common power net.

公开(公告)号：US20200044631A1

公开(公告)日：2020-02-06

申请号：US16152931

申请日：2018-10-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Shyam AGARWAL ,  Sandeep B V ,  Sheetal Y KOCHREKAR ,  Abhishek GHOSH ,  Parvinder Kumar RANA ,  Rohit BISHT

IPC: H03K3/3562 ,  H03K3/012

Abstract: A D flip-flop includes a master block configured to latch an input value of D at one of rising edge and a falling edge of a clock signal, based on the clock signal, the input value of D, and an inverted value of D, and a slave block configured to propagate the input value of D at another one of the falling edge and the rising edge of the clock signal, based on the clock signal.

公开(公告)号：US20200343267A1

公开(公告)日：2020-10-29

申请号：US16924377

申请日：2020-07-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Shyam AGARWAL ,  Abhishek GHOSH ,  Parvinder Kumar RANA

IPC: H01L27/118 ,  H01L21/8238 ,  H01L27/02 ,  H01L27/092

Abstract: Inventive concepts describe a method for high performance standard cell design techniques in FinFET based library using LLE. Inventive concepts describe a fabrication process using a standard FinFET cell layout having double diffusion breaks (DDBs) and single diffusion breaks (SDBs). According to one example embodiment, the method comprises of removing one or more fingers of a P-type FinFet (PFET) from a standard FinFET cell layout. After removing the one or more fingers, a Half-Double Diffusion Break (Half-DDB) is introduced on a N-type FinFET (NFET) side inside a cell boundary using a cut-poly layer. The cut-poly layer not only isolates the PFET and NFET gates and also becomes an integral part of hybrid structure. Further, the removed one or more fingers of PFET gates are converted to two floating PFET gates by shorting a drain terminal and a source terminal of the PFET gate to a common power net.

公开(公告)号：US20200295758A1

公开(公告)日：2020-09-17

申请号：US16533738

申请日：2019-08-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Matthew BERZINS ,  Lalitkumar MOTAGI ,  Shyam AGARWAL

IPC: H03K19/00 ,  G06F1/08 ,  H03C3/09 ,  G06F1/3237

Abstract: According to one general aspect, an apparatus may include a latch circuit configured to, depending in part upon a state or at least one enable signal, pass a clock signal to an output signal. The latch circuit may include an input stage controlled by the clock signal and the enable signal(s). The latch may include an output stage configured to produce the output signal. The input and output stages may share a common transistor controlled by the clock signal.