公开(公告)号：US20200144245A1

公开(公告)日：2020-05-07

申请号：US16238009

申请日：2019-01-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sajal MITTAL ,  Abhishek GHOSH ,  Utkarsh GARG

IPC: H01L27/02 ,  G06F17/50 ,  H01L27/118 ,  H03K19/0185

Abstract: Example embodiments provides a full adder integrated circuit (ADDF) for improving area and power of an integrated circuit (IC). The method includes receiving three input signals and generating three corresponding complementary output signals. Further, the method includes generating an internal signal using two complementary output signals out of the generated three corresponding complementary output signals, and one of the three input signals. Further, the method includes generating an output summation signal using a complementary output signal out of the generated three corresponding complementary output signals, the generated internal signal and a complementary internal signal of the generated internal signal. Further, the method includes generating a carry-out signal using two complementary output signal out of the generated three corresponding complementary output signals, the generated internal signal and the complementary internal signal. Example embodiments herein also provide a four input multiplexer Integrated circuit (MXT4) for reducing the area of the IC.

公开(公告)号：US20200343267A1

公开(公告)日：2020-10-29

申请号：US16924377

申请日：2020-07-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Shyam AGARWAL ,  Abhishek GHOSH ,  Parvinder Kumar RANA

IPC: H01L27/118 ,  H01L21/8238 ,  H01L27/02 ,  H01L27/092

Abstract: Inventive concepts describe a method for high performance standard cell design techniques in FinFET based library using LLE. Inventive concepts describe a fabrication process using a standard FinFET cell layout having double diffusion breaks (DDBs) and single diffusion breaks (SDBs). According to one example embodiment, the method comprises of removing one or more fingers of a P-type FinFet (PFET) from a standard FinFET cell layout. After removing the one or more fingers, a Half-Double Diffusion Break (Half-DDB) is introduced on a N-type FinFET (NFET) side inside a cell boundary using a cut-poly layer. The cut-poly layer not only isolates the PFET and NFET gates and also becomes an integral part of hybrid structure. Further, the removed one or more fingers of PFET gates are converted to two floating PFET gates by shorting a drain terminal and a source terminal of the PFET gate to a common power net.

公开(公告)号：US20240339992A1

公开(公告)日：2024-10-10

申请号：US18202671

申请日：2023-05-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Mitesh GOYAL ,  Hareharan NAGARAJAN ,  Abhishek GHOSH ,  CHIRANSHU BANTHIA

IPC: H03K3/3562 ,  G01R31/3185 ,  H03K3/012

CPC classification number: H03K3/35625 ,  G01R31/318544 ,  G01R31/318594 ,  H03K3/012

Abstract: A multibit flip flop is provided. The multibit flip flop includes: a first stage one-bit flip flop; and a second stage one-bit flip flop, wherein the first stage one-bit flip flop and the second stage one-bit flip flop are configured to share a common clock signal. The first stage one-bit flip flop and the second stage one-bit flip flop are configured to use an inter cell scan input transfer function in a sequential manner. The first stage one-bit flip flop is further configured to provide a scan output signal based on a scan input signal provided at an input port of the first stage one-bit flip flop. The second stage one-bit flip flop is further configured to provide a scan final output signal based on the scan output signal that is provided at an input port of the second stage one-bit flip flop.

公开(公告)号：US20200266185A1

公开(公告)日：2020-08-20

申请号：US16865542

申请日：2020-05-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sajal MITTAL ,  Abhishek GHOSH ,  Utkarsh GARG

IPC: H01L27/02 ,  G06F30/392 ,  H03K19/0185

Abstract: Example embodiments provide a four input multiplexer integrated circuit (MXT4) associated with an integrated circuit (IC) and a method for reducing area and power of an integrated circuit (IC) using a MXT4, the MXT4 including a complementary signal generator circuit configured to receive first and second selection signals and to generate first and second complementary selection signals based on respective ones of the first and the second selection signals; and a p-type metal oxide semiconductor (PMOS) and an n-type metal oxide semiconductor (NMOS) stack switch circuit configured to transmit at least one input signal to an output based on the first and the second selection signals and the first and the second complementary selection signals.

公开(公告)号：US20200044631A1

公开(公告)日：2020-02-06

申请号：US16152931

申请日：2018-10-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Shyam AGARWAL ,  Sandeep B V ,  Sheetal Y KOCHREKAR ,  Abhishek GHOSH ,  Parvinder Kumar RANA ,  Rohit BISHT

IPC: H03K3/3562 ,  H03K3/012

Abstract: A D flip-flop includes a master block configured to latch an input value of D at one of rising edge and a falling edge of a clock signal, based on the clock signal, the input value of D, and an inverted value of D, and a slave block configured to propagate the input value of D at another one of the falling edge and the rising edge of the clock signal, based on the clock signal.