公开(公告)号：US20200044631A1

公开(公告)日：2020-02-06

申请号：US16152931

申请日：2018-10-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Shyam AGARWAL ,  Sandeep B V ,  Sheetal Y KOCHREKAR ,  Abhishek GHOSH ,  Parvinder Kumar RANA ,  Rohit BISHT

IPC: H03K3/3562 ,  H03K3/012

Abstract: A D flip-flop includes a master block configured to latch an input value of D at one of rising edge and a falling edge of a clock signal, based on the clock signal, the input value of D, and an inverted value of D, and a slave block configured to propagate the input value of D at another one of the falling edge and the rising edge of the clock signal, based on the clock signal.

公开(公告)号：US10715118B2

公开(公告)日：2020-07-14

申请号：US16101789

申请日：2018-08-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Shyam Agarwal ,  Sandeep B V ,  Shreyas Samraksh Jayaprakash ,  Abhishek Kumar Ghosh ,  Parvinder Kumar Rana

IPC: G11C11/41 ,  H03K3/3562 ,  H01L27/11 ,  H03K19/017 ,  H03K3/012

Abstract: Various example embodiments herein disclose a flip-flop including a master latch comprising one of: a plurality of P-type metal-oxide-semiconductor (PMOS) and a plurality of N-type metal-oxide-semiconductor (NMOS). A slave latch includes one of: a plurality of PMOS and a plurality of NMOS. An inverted clock signal input is communicatively connected with the master latch and the slave latch. The master latch includes a single pre-charge node. The single pre-charge node sets up a data capture path in the flip flop. Data is stored in the master latch and the slave latch via the pre-charge node.

公开(公告)号：US20190058461A1

公开(公告)日：2019-02-21

申请号：US16101789

申请日：2018-08-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Shyam AGARWAL ,  Sandeep B V ,  Shreyas Samraksh Jayaprakash ,  Abhishek Kumar Ghosh ,  Parvinder Kumar Rana

IPC: H03K3/3562 ,  H01L27/11 ,  H03K3/012 ,  H03K19/017 ,  G11C11/41

Abstract: Various example embodiments herein disclose a flip-flop including a master latch comprising one of: a plurality of P-type metal-oxide-semiconductor (PMOS) and a plurality of N-type metal-oxide-semiconductor (NMOS). A slave latch includes one of: a plurality of PMOS and a plurality of NMOS. An inverted clock signal input is communicatively connected with the master latch and the slave latch. The master latch includes a single pre-charge node. The single pre-charge node sets up a data capture path in the flip flop. Data is stored in the master latch and the slave latch via the pre-charge node.