公开(公告)号：US20200044631A1

公开(公告)日：2020-02-06

申请号：US16152931

申请日：2018-10-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Shyam AGARWAL ,  Sandeep B V ,  Sheetal Y KOCHREKAR ,  Abhishek GHOSH ,  Parvinder Kumar RANA ,  Rohit BISHT

IPC: H03K3/3562 ,  H03K3/012

Abstract: A D flip-flop includes a master block configured to latch an input value of D at one of rising edge and a falling edge of a clock signal, based on the clock signal, the input value of D, and an inverted value of D, and a slave block configured to propagate the input value of D at another one of the falling edge and the rising edge of the clock signal, based on the clock signal.