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    SYSTEM AND METHOD FOR IMPROVING SCAN HOLD-TIME VIOLATION AND LOW VOLTAGE OPERATION IN SEQUENTIAL CIRCUIT
    1.
    发明申请
    SYSTEM AND METHOD FOR IMPROVING SCAN HOLD-TIME VIOLATION AND LOW VOLTAGE OPERATION IN SEQUENTIAL CIRCUIT 审中-公开

    公开(公告)号：US20180342287A1

    公开(公告)日：2018-11-29

    申请号：US15680198

    申请日：2017-08-17

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Matthew BERZINS

    IPC: G11C11/417 ,  H03K3/037

    CPC classification number: G11C11/417 ,  H03K3/0372

    Abstract: According to one general aspect, an apparatus may include a flip-flop circuit. The flip-flop circuit may include a selection circuit, a memory element circuit, a clock circuit. The selection circuit to select, as the selected input signal, between at least two input signals. The memory element circuit synchronously controlled by a clock signal, and configured to store the selected input signal. The clock circuit configured to output, at least, an earlier version of the clock signal and a later version of the clock signal. The selection circuit is configured to be synchronously controlled, at least in part, by the earlier version of the clock signal such that the selected input signal is held stable when being read by the memory element circuit.

    NOVEL METHOD FOR REDUCING POWER CONSUMPTION IN SCANNABLE FLIP-FLOPS WITHOUT ADDITIONAL CIRCUITRY
    2.
    发明申请
    NOVEL METHOD FOR REDUCING POWER CONSUMPTION IN SCANNABLE FLIP-FLOPS WITHOUT ADDITIONAL CIRCUITRY 审中-公开

    公开(公告)号：US20200292617A1

    公开(公告)日：2020-09-17

    申请号：US16523993

    申请日：2019-07-26

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Matthew BERZINS

    IPC: G01R31/3185 ,  G01R31/317

    Abstract: According to one general aspect, an apparatus may include a first power signal having a high voltage. The apparatus may include a second power signal having a low voltage. The apparatus may include a third power signal having a voltage configured to switch between the high voltage and the low voltage. The apparatus may include a latching circuit powered by the first power signal and the second power signal. The apparatus may include a selection circuit configured to select between, at least, a first data signal and a second data signal, and powered by the first power signal, the second power signal, and the third power signal.

    SYSTEM AND METHOD FOR IMPROVING SCAN HOLD-TIME VIOLATION AND LOW VOLTAGE OPERATION IN SEQUENTIAL CIRCUIT
    3.
    发明申请
    SYSTEM AND METHOD FOR IMPROVING SCAN HOLD-TIME VIOLATION AND LOW VOLTAGE OPERATION IN SEQUENTIAL CIRCUIT 审中-公开

    公开(公告)号：US20190221255A1

    公开(公告)日：2019-07-18

    申请号：US16358681

    申请日：2019-03-19

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Matthew BERZINS

    IPC: G11C11/417 ,  H03K3/037

    CPC classification number: G11C11/417 ,  H03K3/0372

    Abstract: According to one general aspect, an apparatus may include a flip-flop circuit. The flip-flop circuit may include a selection circuit, a memory element circuit, a clock circuit. The selection circuit to select, as the selected input signal, between at least two input signals. The memory element circuit synchronously controlled by a clock signal, and configured to store the selected input signal. The clock circuit configured to output, at least, an earlier version of the clock signal and a later version of the clock signal. The selection circuit is configured to be synchronously controlled, at least in part, by the earlier version of the clock signal such that the selected input signal is held stable when being read by the memory element circuit.

    LOW POWER TOGGLE LATCH-BASED FLIP-FLOP INCLUDING INTEGRATED CLOCK GATING LOGIC
    4.
    发明申请
    LOW POWER TOGGLE LATCH-BASED FLIP-FLOP INCLUDING INTEGRATED CLOCK GATING LOGIC 有权
    低功率钳口基于FLIP-FLOP包括集成时钟提升逻辑

    公开(公告)号：US20150200652A1

    公开(公告)日：2015-07-16

    申请号：US14267883

    申请日：2014-05-01

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Matthew BERZINS ,  Christina WELLS

    IPC: H03K3/012 ,  H03K3/037

    CPC classification number: H03K3/012 ,  H03K3/037 ,  H03K3/0372

    Abstract: Inventive aspects include integrated clock gating logic that can generate an internal glitch-free clock signal. Inventive aspects further include a toggle latch that is coupled to the integrated clock gating logic. The toggle latch can receive the internal clock signal from the integrated clock gating logic. The toggle latch can toggle and latch a data value responsive to the internal clock signal. The integrated clock gating logic can include a latch to latch a clock gating logic signal responsive to a clock signal. The clock gating logic signal can cause the internal clock signal to be quiescent when the input data to the flip-flop remains constant, thereby conserving power consumption.

    Abstract translation: 发明方面包括可产生内部无毛刺时钟信号的集成时钟门控逻辑。 发明方面还包括耦合到集成时钟选通逻辑的触发锁存器。 触发锁存器可以从集成时钟门控逻辑接收内部时钟信号。 触发锁存器可以响应于内部时钟信号切换并锁存数据值。 集成时钟门控逻辑可以包括锁存器，以响应于时钟信号锁存时钟门控逻辑信号。 当触发器的输入数据保持不变时，时钟选通逻辑信号可能导致内部时钟信号静止，从而节省功耗。

    POWER GRID AND STANDARD CELL CO-DESIGN STRUCTURE AND METHODS THEREOF
    6.
    发明申请
    POWER GRID AND STANDARD CELL CO-DESIGN STRUCTURE AND METHODS THEREOF 审中-公开

    公开(公告)号：US20190385999A1

    公开(公告)日：2019-12-19

    申请号：US16274229

    申请日：2019-02-12

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Matthew BERZINS ,  Andrew Paul HOOVER ,  Christopher Alan PEURA

    IPC: H01L27/02 ,  G06F17/50 ,  H01L29/423 ,  H01L23/522 ,  H01L27/118

    Abstract: According to one general aspect, an apparatus may include a metal layer having a metal pitch between metal elements, and a gate electrode layer having a gate pitch between gate electrode elements, wherein the gate electrode pitch is a ratio of the metal pitch. The apparatus may include at least two power rails coupled, by via staples, with the metal layer, wherein the via staples at least partially overlap one or more of the gate electrode elements. The apparatus may include even and odd pluralities of standard cells, each respectively located in even/odd placement sites wherein portions of the standard cells that carry signals within the metal layer do not connect to the via staples.

    LOW POWER INTEGRATED CLOCK GATING CELL USING CONTROLLED INVERTED CLOCK
    7.
    发明申请
    LOW POWER INTEGRATED CLOCK GATING CELL USING CONTROLLED INVERTED CLOCK 审中-公开

    公开(公告)号：US20180287610A1

    公开(公告)日：2018-10-04

    申请号：US15629729

    申请日：2017-06-21

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： James Jung LIM ,  Matthew BERZINS

    IPC: H03K19/00 ,  H03K3/012 ,  H03K3/356

    CPC classification number: H03K19/0013 ,  H03K23/58

    Abstract: Embodiments include an integrated clock gating (ICG) cell. The low power ICG cell may include an input condition determination circuit configured to generate a temporary inverted clock signal and an inverted output signal. The low power ICG cell may include an enable control logic circuit configured to receive the temporary inverted clock signal and the inverted output signal from the input condition determination circuit. The low power ICG cell may include a latch circuit coupled to the enable control logic circuit and configured to latch an input value dependent on at least the inverted output signal and the temporary inverted clock signal. The input condition determination circuit is configured to generate the temporary inverted clock signal only when it is needed.

    LAYOUT CONNECTION ISOLATION TECHNIQUE FOR IMPROVING IMMUNITY TO JITTER AND VOLTAGE DROP IN A STANDARD CELL
    8.
    发明申请
    LAYOUT CONNECTION ISOLATION TECHNIQUE FOR IMPROVING IMMUNITY TO JITTER AND VOLTAGE DROP IN A STANDARD CELL 审中-公开

    公开(公告)号：US20200020678A1

    公开(公告)日：2020-01-16

    申请号：US16150249

    申请日：2018-10-02

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Matthew BERZINS ,  Charles A. CORNELL

    IPC: H01L27/02 ,  H01L23/528 ,  H01L23/522 ,  H03K19/003

    Abstract: A standard cell architecture provides an improved immunity to power-supply voltage-drop, does not induce power-supply voltage drop on a continuous-row power rail of a standard cell, and maintains standard-cell environment compatibility. A circuit includes a first metal layer and a second metal layer that are formed different distances above a substrate. At least one first standard cell drives a first timing signal and includes at least one transistor receiving power from a first power rail in the first metal layer. At least one second standard cell drives a second timing signal and includes at least one transistor receiving power from a second power rail in the second metal layer. The second power rail has both a low peak noise level and a resistance that is lower than that of the first metal layer.

    SYSTEM AND METHOD FOR REDUCING POWER CONSUMPTION IN SCANNABLE CIRCUIT
    9.
    发明申请
    SYSTEM AND METHOD FOR REDUCING POWER CONSUMPTION IN SCANNABLE CIRCUIT 审中-公开

    公开(公告)号：US20180340979A1

    公开(公告)日：2018-11-29

    申请号：US15663580

    申请日：2017-07-28

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Matthew BERZINS

    IPC: G01R31/3185 ,  H03K19/00 ,  H03K19/173

    Abstract: A scannable circuit element includes a data path and a scan-data path that are respectively selected in response to a first operational mode and a second operational mode. The scan-data path includes an input element having an input node, an output node, a first power node and a second power node. A signal path between the input node and the output node is part of the scan-data path. The first power node is coupled to a first voltage potential, and the second power node is coupled to a mode-control signal that is at substantially the first voltage potential in the first operational mode and that is at substantially a second voltage potential in the second operational mode. In the second operational mode, the scannable element exhibits no switching current and no leakage current.

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