ZERO DIFFUSION BREAK
    1.
    发明公开

    公开(公告)号:US20230161940A1

    公开(公告)日:2023-05-25

    申请号:US17863382

    申请日:2022-07-12

    CPC classification number: G06F30/3953 G06F30/392

    Abstract: A standard cell in a Place and Route (PNR) library of standard cells includes a cell boundary and cell configuration information. The cell boundary includes a first edge and a second edge that is opposite the first edge. The cell configuration information indicates a power connection configuration to be used with a second standard cell when the standard cell is placed next to the second standard cell in a layout in a PNR environment, such that at least one transistor source electrode is physically shared between the standard cell and the second standard cell. The cell configuration information may be edge identifier information for the first edge and/or the second edge of the first standard cell. The power connection configuration may also indicate that the power connection configuration for the first edge and/or the second edge is outside the cell boundary for the standard cell.

    POWER GRID AND STANDARD CELL CO-DESIGN STRUCTURE AND METHODS THEREOF

    公开(公告)号:US20190385999A1

    公开(公告)日:2019-12-19

    申请号:US16274229

    申请日:2019-02-12

    Abstract: According to one general aspect, an apparatus may include a metal layer having a metal pitch between metal elements, and a gate electrode layer having a gate pitch between gate electrode elements, wherein the gate electrode pitch is a ratio of the metal pitch. The apparatus may include at least two power rails coupled, by via staples, with the metal layer, wherein the via staples at least partially overlap one or more of the gate electrode elements. The apparatus may include even and odd pluralities of standard cells, each respectively located in even/odd placement sites wherein portions of the standard cells that carry signals within the metal layer do not connect to the via staples.

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