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    Bitline precharge system for a semiconductor memory device
    1.
    发明授权
    Bitline precharge system for a semiconductor memory device 有权

    公开(公告)号：US11410720B2

    公开(公告)日：2022-08-09

    申请号：US16952712

    申请日：2020-11-19

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Lava Kumar Pulluru ,  Ankur Gupta ,  Parvinder Kumar Rana

    IPC: G11C11/419

    Abstract: A bitline precharge system is provided for a semiconductor memory device. The bitline precharge system comprises a voltage comparator circuit to output a reference voltage signal based on an input wordline voltage supply level (VDDWL), and a periphery power supply voltage (VDDP) level. A voltage control circuit is electrically coupled to a periphery power supply and the voltage comparator circuit to output a precharge voltage (VDDM) level based on the reference voltage signal and the periphery power supply voltage (VDDP) level. A bitline precharge circuit is electrically coupled to the voltage control circuit and a plurality of bitlines of the memory device to precharge the plurality of bitlines based on the precharge voltage (VDDM) level in response to a precharge enable signal during one of a read operation to read data from the memory device and a write operation to write data from the memory device. Further, the at least one bitline is discharged from the precharge voltage (VDDM) level during at least one of the read operation or the write operation.

    Level shifter circuits
    2.
    发明授权
    Level shifter circuits 有权

    公开(公告)号：US11290092B1

    公开(公告)日：2022-03-29

    申请号：US17175818

    申请日：2021-02-15

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Ankur Gupta ,  Lava Kumar Pulluru ,  Parvinder Kumar Rana

    IPC: G11C11/40 ,  H03K3/356 ,  H03K19/0185 ,  G11C11/419 ,  G11C11/412

    Abstract: An apparatus includes a NMOS transistor having a drain, a first PMOS transistor having a drain connected to the drain of the NMOS transistor, a level shifter having an input and an output, the input of the level shifter being connected to the drain of the NMOS transistor and the drain of the first PMOS transistor, a first digital logic circuit having a drain and a gate, a first inverter having an input connected to the Aoutput of the level shifter and the drain of the first digital logic circuit, and a second digital logic circuit having an output connected to the gate of the first digital logic circuit, at least one condition being set in the apparatus during a read operation.

    CMOS-ASSISTED INSIDE-OUT DYNAMIC VISION SENSOR TRACKING FOR LOW POWER MOBILE PLATFORMS
    3.
    发明申请
    CMOS-ASSISTED INSIDE-OUT DYNAMIC VISION SENSOR TRACKING FOR LOW POWER MOBILE PLATFORMS 有权

    公开(公告)号：US20210075964A1

    公开(公告)日：2021-03-11

    申请号：US16953111

    申请日：2020-11-19

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Michael Sapienza ,  Ankur Gupta ,  Abhijit Bendale ,  Fannie Fontanel

    IPC: H04N5/232 ,  H04N5/343 ,  G02B27/01 ,  H04N5/357 ,  H04N5/374 ,  G06T7/11 ,  G06K9/62 ,  G06T15/00 ,  G06T15/10 ,  G06T19/00

    Abstract: An untethered apparatus for performing inside-out device tracking based on visual-inertial simultaneous location and mapping (SLAM) includes a dynamic vision sensor (DVS) configured to output an asynchronous stream of sensor event data, an inertial measurement unit (IMU) sensor configured to collect IMU data associated with motion of the apparatus at a predetermined interval, a processor and a memory. The memory contains instructions, which when executed by the processor, cause the apparatus to accumulate DVS sensor output over a sliding time window, the sliding time window including the predetermined interval, apply a motion correction to the accumulated DVS sensor output, the motion correction based on the IMU data collected over the predetermined interval, generate an event-frame histogram of DVS sensor events based on the motion correction, and provide the event-frame histogram of the DVS sensor events and the IMU data to a visual inertial SLAM pipeline.

    Methods and apparatuses to reduce power dissipation in a static random access memory (SRAM) device
    4.
    发明授权
    Methods and apparatuses to reduce power dissipation in a static random access memory (SRAM) device 有权

    公开(公告)号：US10522218B2

    公开(公告)日：2019-12-31

    申请号：US16190278

    申请日：2018-11-14

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Parvinder Kumar Rana ,  Lava Kumar Pulluru ,  Shuvadeep Kumar ,  Ankur Gupta

    IPC: G11C11/419 ,  G11C11/418

    Abstract: Embodiments herein provide a method for reducing power dissipation in a Static Random Access Memory (SRAM) device. The method includes determining, by the tracking circuit, whether at least one SRAM Bit-Cell discharges power from at least one BL exceeding a pre-defined voltage level required for a sense amplifier to perform a read operation. Furthermore, the method includes reducing, by the WL driver, the power discharged from the at least one BL by controlling a WL voltage power supply switch of the WL driver using a SAE signal and adjusting a pulse width of the at least one WL to pull down the at least one WL using a NMOS circuit when the at least one SRAM Bit-Cell discharges the power from the at least one BL exceeding the pre-defined voltage level.

    CAMERA POSE DETERMINATION AND TRACKING
    6.
    发明申请
    CAMERA POSE DETERMINATION AND TRACKING 审中-公开

    公开(公告)号：US20190096081A1

    公开(公告)日：2019-03-28

    申请号：US15962757

    申请日：2018-04-25

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Ankur Gupta ,  Michael Sapienza ,  Fannie Fontanel ,  Abhijit Z. Bendale ,  Pranav Mistry

    IPC: G06T7/70 ,  G06T5/00

    Abstract: A system for determining and tracking camera pose includes a dynamic vision sensor (DVS) configured to generate a current DVS image, an inertial measurement unit (IMU) configured to generate inertial data, and a memory. The memory is configured to store a 3-dimensional (3D) map of a known 3D environment. The system may also include a processor coupled to the memory. The processor is configured to initiate operations including determining a current camera pose for the DVS based on the current DVS image, the inertial data, the 3D map, and a prior camera pose.

    CAMERA POSE AND PLANE ESTIMATION USING ACTIVE MARKERS AND A DYNAMIC VISION SENSOR
    7.
    发明申请
    CAMERA POSE AND PLANE ESTIMATION USING ACTIVE MARKERS AND A DYNAMIC VISION SENSOR 审中-公开

    公开(公告)号：US20190096068A1

    公开(公告)日：2019-03-28

    申请号：US15962841

    申请日：2018-04-25

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Fannie Fontanel ,  Ankur Gupta ,  Michael Sapienza ,  Abhijit Z. Bendale ,  Pranav Mistry

    IPC: G06T7/20

    Abstract: A method of camera pose and plane estimation may include detecting a marker within a 3-dimensional (3D) environment by detecting, using a Dynamic Vision Sensor (DVS), a first plurality of light sources arranged in a known shape and blinking at a first frequency, wherein the known shape corresponds to the marker, determining an orientation and an identity of the marker based upon detecting, using the DVS, a second plurality of light sources corresponding to the marker and blinking at a second frequency different from the first frequency. A camera pose for the DVS may be determined based upon the known shape, the orientation, and the identity of the marker using the processor.

    AUTOREGRESSIVE CONTENT RENDERING FOR TEMPORALLY COHERENT VIDEO GENERATION
    9.
    发明公开
    AUTOREGRESSIVE CONTENT RENDERING FOR TEMPORALLY COHERENT VIDEO GENERATION 审中-公开

    公开(公告)号：US20240354996A1

    公开(公告)日：2024-10-24

    申请号：US18428487

    申请日：2024-01-31

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Varun Menon ,  Siddarth Ravichandran ,  Ankur Gupta ,  Hyun Jae Kang ,  Sajid Sadi

    IPC: G06T9/00 ,  G06V10/764

    CPC classification number: G06T9/00 ,  G06V10/764

    Abstract: Autoregressive content rendering for temporally coherent video generation includes generating, by an autoencoder, a plurality of predicted images. The plurality of predicted images is fed back to the autoencoder network. The plurality of predicted images may be encoded by the autoencoder network to generate a plurality of encoded predicted images. The autoencoder network encodes a plurality of keypoint images to generate a plurality of encoded keypoint images. One or more predicted images of the plurality of predicted images are generated by the autoencoder network by decoding a selected encoded keypoint image of the plurality of encoded keypoint images with an encoded predicted image of the plurality of encoded predicted images of a prior iteration of the autoencoder network.

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