公开(公告)号：US20240321324A1

公开(公告)日：2024-09-26

申请号：US18375805

申请日：2023-10-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Poornima Venkatasubramanian ,  Gopi Sunanth Kumar Gogineni ,  Puneet Suri ,  Lava Kumar Pulluru ,  Karthikeyan Somashekara ,  Manish Chandra Joshi

IPC: G11C7/04 ,  G11C7/14 ,  G11C7/22

CPC classification number: G11C7/04 ,  G11C7/14 ,  G11C7/222

Abstract: A memory device, includes a voltage and temperature sensing circuit configured to generate a Pull Down (PD) signal that varies based on upon at least one of a voltage and temperature at the memory device; and primary pull down paths provided with secondary pull down paths, wherein the primary pull down paths are provided separately at a Dummy Read Bit line (DRBL) and a Dummy Global Read Bit line (DGRBL), wherein the secondary pull down paths are provided separately for the DRBL and the DGRBL parallel to the respective primary pull down paths. The voltage and temperature sensing circuit is configured to perform at least one of: controlling at least one of the secondary pull down paths based on a voltage of the PD signal; varying a discharge time of at least one of the dummy bit-lines based on the voltage of the PD signal; and generating an early reset signal at one of a high temperature condition and a high voltage condition based on the voltage of the PD signal.