公开(公告)号：US12087387B2

公开(公告)日：2024-09-10

申请号：US17750690

申请日：2022-05-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Lava Kumar Pulluru ,  Poornima Venkatasubramanian ,  Manish Chandra Joshi ,  Ved Prakash ,  Pushp Khatter

IPC: G11C7/10 ,  H03K3/037

CPC classification number: G11C7/1039 ,  G11C7/1066 ,  G11C7/1093 ,  H03K3/0372

Abstract: A memory device includes at least one bitcell; read circuitry coupled to the at least one bitcell; and screening circuitry coupled to the read circuitry, wherein the screening circuitry includes a master slave flip-flop configured to store an output of the at least one bitcell during a read operation of the memory device, wherein the master slave flip-flop includes a master latch and a slave latch; and a DOUT window controller coupled to the master slave flip-flop and configured to generate and control a master clock signal for the master latch to determine if the at least one bitcell is a weak bitcell; and generate and control a slave clock signal for the slave latch to enable toggling of the output of the at least one bitcell during a transparent window between the master clock signal and the slave clock signal.

公开(公告)号：US20240347104A1

公开(公告)日：2024-10-17

申请号：US18378598

申请日：2023-10-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Lava Kumar Pulluru ,  Manish Chandra Joshi ,  Parvinder Kumar Rana ,  Poornima Venkatasubramanian ,  Ved Prakash ,  Chaitanya Vavilla

IPC: G11C11/419

CPC classification number: G11C11/419

Abstract: A memory device and its operation reduce the impact of a parasitic wire Resistance and Capacitance (RC) in the memory device. At least one of a rise transition and a fall transition of a signal transmitted by a long metal line is sensed by a sense circuit of a signal boosting circuit. At least one of a Pull Up (PU) circuit and a Pull Down (PD) circuit of the signal boosting circuit is enabled to speed-up one or both of the rise transition and the fall transition of the signal transmitted by the long metal line. The duration of an operation of one of the PU circuit and the PD circuit may be controlled using a control signal.

公开(公告)号：US12205636B2

公开(公告)日：2025-01-21

申请号：US18163584

申请日：2023-02-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Poornima Venkatasubramanian ,  Pushp Khatter ,  Lava Kumar Pulluru ,  Manish Chandra Joshi ,  Ved Prakash ,  Anurag Kumar ,  Surendra Deshmukh

IPC: G11C11/00 ,  G11C11/412 ,  G11C11/419

Abstract: A write assist circuit includes a first power control circuit and second power control circuit, each comprising a first switch and second switch. The first switch of first power control circuit has first drive strength and is configured to be controlled by a column select line, a power control line, a first bit line, and a power supply. The first switch of the second power control circuit has the first drive strength and is configured to be controlled by the column select line, the power control line, a second bit line, and the power supply. The second switch has a second drive strength and is configured to be controlled by the power control line. The first switches are configured to be controlled using input data on first- and second-bit line, respectively, for altering power supply to first inverter and second inverter of SRAM bitcell.

公开(公告)号：US20240321324A1

公开(公告)日：2024-09-26

申请号：US18375805

申请日：2023-10-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Poornima Venkatasubramanian ,  Gopi Sunanth Kumar Gogineni ,  Puneet Suri ,  Lava Kumar Pulluru ,  Karthikeyan Somashekara ,  Manish Chandra Joshi

IPC: G11C7/04 ,  G11C7/14 ,  G11C7/22

CPC classification number: G11C7/04 ,  G11C7/14 ,  G11C7/222

Abstract: A memory device, includes a voltage and temperature sensing circuit configured to generate a Pull Down (PD) signal that varies based on upon at least one of a voltage and temperature at the memory device; and primary pull down paths provided with secondary pull down paths, wherein the primary pull down paths are provided separately at a Dummy Read Bit line (DRBL) and a Dummy Global Read Bit line (DGRBL), wherein the secondary pull down paths are provided separately for the DRBL and the DGRBL parallel to the respective primary pull down paths. The voltage and temperature sensing circuit is configured to perform at least one of: controlling at least one of the secondary pull down paths based on a voltage of the PD signal; varying a discharge time of at least one of the dummy bit-lines based on the voltage of the PD signal; and generating an early reset signal at one of a high temperature condition and a high voltage condition based on the voltage of the PD signal.