公开(公告)号：US20240347104A1

公开(公告)日：2024-10-17

申请号：US18378598

申请日：2023-10-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Lava Kumar Pulluru ,  Manish Chandra Joshi ,  Parvinder Kumar Rana ,  Poornima Venkatasubramanian ,  Ved Prakash ,  Chaitanya Vavilla

IPC: G11C11/419

CPC classification number: G11C11/419

Abstract: A memory device and its operation reduce the impact of a parasitic wire Resistance and Capacitance (RC) in the memory device. At least one of a rise transition and a fall transition of a signal transmitted by a long metal line is sensed by a sense circuit of a signal boosting circuit. At least one of a Pull Up (PU) circuit and a Pull Down (PD) circuit of the signal boosting circuit is enabled to speed-up one or both of the rise transition and the fall transition of the signal transmitted by the long metal line. The duration of an operation of one of the PU circuit and the PD circuit may be controlled using a control signal.