公开(公告)号：US20160183379A1

公开(公告)日：2016-06-23

申请号：US14579735

申请日：2014-12-22

Applicant: QUALCOMM Incorporated

Inventor： Young Kyu Song ,  Hong Bok We ,  Kyu-Pyung Hwang

IPC: H05K1/18 ,  H05K3/32

CPC classification number: H05K1/185 ,  H01G4/224 ,  H01G4/232 ,  H01G4/30 ,  H01G4/33 ,  H01G4/40 ,  H01L2224/16227 ,  H01L2924/15311 ,  H05K3/4602 ,  H05K2201/10015 ,  H05K2203/1469

Abstract: A substrate that includes a first dielectric layer and a capacitor embedded in the first dielectric layer. The capacitor includes a base portion, a first terminal and a second terminal. The first terminal is located on a first surface of the base portion, where the first terminal is the only terminal on the first surface of the base portion. The second terminal is located on a second surface of the base portion. The second surface is opposite to the first surface. The second terminal is the only terminal on the second surface of the base portion. In some implementations, the capacitor further includes a first base metal layer located between the first surface of the base portion and the first terminal. In some implementations, the capacitor also includes a second base metal layer located between the second surface of the base portion and the second terminal.

Abstract translation: 一种衬底，其包括第一介电层和嵌入第一介电层中的电容器。 电容器包括基部，第一端子和第二端子。 第一端子位于基部的第一表面上，其中第一端子是基部的第一表面上的唯一端子。 第二端子位于基部的第二表面上。 第二表面与第一表面相对。 第二端子是基部的第二表面上的唯一端子。 在一些实施方式中，电容器还包括位于基部的第一表面和第一端之间的第一基底金属层。 在一些实施方式中，电容器还包括位于基部的第二表面和第二端之间的第二基底金属层。

公开(公告)号：US20160163628A1

公开(公告)日：2016-06-09

申请号：US14563854

申请日：2014-12-08

Applicant: QUALCOMM Incorporated

Inventor： Hong Bok We ,  Kyu-Pyung Hwang ,  Young Kyu Song ,  Dong Wook Kim

IPC: H01L23/498 ,  H01L23/66 ,  H01L21/48 ,  H05K1/16

CPC classification number: H01L23/49827 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/4824 ,  H01L23/49811 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/49894 ,  H01L23/66 ,  H01L24/83 ,  H01L2223/6622 ,  H01L2224/16225 ,  H01L2224/16265 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/92125 ,  H01L2924/15174 ,  H01L2924/15311 ,  H05K1/162 ,  H01L2924/00

Abstract: A package substrate that includes a first portion and a redistribution portion. The first portion is configured to operate as a capacitor. The first portion includes a first dielectric layer, a first set of metal layers in the dielectric layer, a first via in the dielectric layer, a second set of metal layers in the dielectric layer, and a second via in the dielectric layer. The first via is coupled to the first set of metal layers. The first via and the first set of metal layers are configured to provide a first electrical path for a ground signal. The second via is coupled to the second set of metal layers. The second via and the second set of metal layers are configured to provide a second electrical path for a power signal. The redistribution portion includes a second dielectric layer, and a set of interconnects.

Abstract translation: 一种封装基板，包括第一部分和再分配部分。 第一部分被配置为作为电容器工作。 第一部分包括第一电介质层，电介质层中的第一组金属层，电介质层中的第一通孔，介电层中的第二组金属层和介电层中的第二通孔。 第一通孔耦合到第一组金属层。 第一通孔和第一组金属层被配置成为接地信号提供第一电路径。 第二通孔耦合到第二组金属层。 第二通孔和第二组金属层被配置成为功率信号提供第二电路径。 再分配部分包括第二介电层和一组互连。

公开(公告)号：US09269610B2

公开(公告)日：2016-02-23

申请号：US14253798

申请日：2014-04-15

Applicant: QUALCOMM Incorporated

Inventor： Hong Bok We ,  Chin-Kwan Kim ,  Dong Wook Kim ,  Jae Sik Lee ,  Kyu-Pyung Hwang ,  Young Kyu Song

IPC: H01L21/44 ,  H01L21/768 ,  H01L23/498 ,  H01L21/48 ,  H01L23/528 ,  H01L23/532

CPC classification number: H01L21/768 ,  H01L21/4857 ,  H01L21/76802 ,  H01L21/76838 ,  H01L21/76879 ,  H01L21/76885 ,  H01L23/49822 ,  H01L23/5283 ,  H01L23/5329 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/16225 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/014

Abstract: An integrated circuit (IC) substrate that includes a second patterned metal layer formed in between a first patterned metal layer is disclosed. A dielectric layer formed on the first patterned metal layer separates the two metal layers. A non-conductive layer is formed on the dielectric layer and the second patterned metal layer.

Abstract translation: 公开了一种集成电路（IC）基板，其包括形成在第一图案化金属层之间的第二图案化金属层。 形成在第一图案化金属层上的电介质层分离两个金属层。 在介电层和第二图案化金属层上形成非导电层。

公开(公告)号：US20150340425A1

公开(公告)日：2015-11-26

申请号：US14283980

申请日：2014-05-21

Applicant: QUALCOMM Incorporated

Inventor： Hong Bok We ,  Kyu-Pyung Hwang ,  Young Kyu Song ,  Dong Wook Kim

IPC: H01L49/02 ,  H05K1/18 ,  H05K3/46 ,  H01L23/498

CPC classification number: H01L28/40 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/50 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/16227 ,  H01L2924/15311 ,  H05K1/185 ,  H05K3/4602 ,  H01L2924/014

Abstract: A package substrate is provided that includes a core substrate and a capacitor embedded in the core substrate including a first side. The capacitor includes a first electrode and a second electrode disposed at opposite ends of the capacitor. The package also includes a first power supply metal plate extending laterally in the core substrate. The first power supply metal plate is disposed directly on the first electrode of the capacitor from the first side of the core substrate. A first via extending perpendicular to the first metal plate and connected to the first power supply metal plate from the first side of the core substrate.

Abstract translation: 提供一种封装基板，其包括芯基板和嵌入在包括第一侧的芯基板中的电容器。 电容器包括设置在电容器的相对端的第一电极和第二电极。 封装还包括在芯基板中横向延伸的第一电源金属板。 第一电源金属板从芯基板的第一侧直接设置在电容器的第一电极上。 第一通孔，其垂直于第一金属板延伸并从芯基板的第一侧连接到第一电源金属板。

公开(公告)号：US20150325509A1

公开(公告)日：2015-11-12

申请号：US14273882

申请日：2014-05-09

Applicant: QUALCOMM Incorporated

Inventor： Hong Bok We ,  Dong Wook Kim ,  Jae Sik Lee ,  Shiqun Gu ,  Ratibor Radojcic

IPC: H01L23/498 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H05K1/11 ,  H01L23/522 ,  H01L23/528 ,  H01L21/311 ,  H05K1/09 ,  H01L21/78 ,  H01L25/065

CPC classification number: H01L23/49827 ,  H01L21/31127 ,  H01L21/561 ,  H01L21/565 ,  H01L21/78 ,  H01L23/3107 ,  H01L23/3128 ,  H01L23/498 ,  H01L23/49866 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/5385 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L24/97 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13118 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/16235 ,  H01L2224/81411 ,  H01L2224/81424 ,  H01L2224/81439 ,  H01L2224/81444 ,  H01L2224/81447 ,  H01L2224/81455 ,  H01L2224/81466 ,  H01L2224/81484 ,  H01L2224/81801 ,  H01L2224/81815 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06548 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2225/107 ,  H01L2924/01014 ,  H01L2924/01029 ,  H01L2924/141 ,  H01L2924/143 ,  H01L2924/1433 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/157 ,  H01L2924/15788 ,  H01L2924/1579 ,  H01L2924/20648 ,  H01L2924/3511 ,  H05K1/09 ,  H05K1/115 ,  H05K2201/09563 ,  H01L2924/014 ,  H01L2224/81

Abstract: A substrate block is provided that has an increased width. The substrate block comprises two substrate bars, and the substrate bars each comprise a substrate and a plurality of filled vias through the substrate. The substrate block may be used to manufacture package substrates, and these package substrate may be incorporated into a PoP structure. The package substrate includes a carrier having a plurality of vertical interconnections and a bar coupled to the vertical interconnections.

Abstract translation: 提供具有增加的宽度的衬底块。 衬底块包括两个衬底条，并且衬底条各自包括衬底和穿过衬底的多个填充的通孔。 衬底块可以用于制造封装衬底，并且这些封装衬底可以并入PoP结构中。 封装衬底包括具有多个垂直互连的载体和耦合到垂直互连的条。

公开(公告)号：US20150294933A1

公开(公告)日：2015-10-15

申请号：US14253798

申请日：2014-04-15

Applicant: QUALCOMM Incorporated

Inventor： Hong Bok We ,  Chin-Kwan Kim ,  Dong Wook Kim ,  Jae Sik Lee ,  Kyu-Pyung Hwang ,  Young Kyu Song

IPC: H01L23/528 ,  H01L23/522 ,  H01L21/768 ,  H01L23/532

CPC classification number: H01L21/768 ,  H01L21/4857 ,  H01L21/76802 ,  H01L21/76838 ,  H01L21/76879 ,  H01L21/76885 ,  H01L23/49822 ,  H01L23/5283 ,  H01L23/5329 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/16225 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/014

Abstract: An integrated circuit (IC) substrate that includes a second patterned metal layer formed in between a first patterned metal layer is disclosed. A dielectric layer formed on the first patterned metal layer separates the two metal layers. A non-conductive layer is formed on the dielectric layer and the second patterned metal layer.

Abstract translation: 公开了一种集成电路（IC）基板，其包括形成在第一图案化金属层之间的第二图案化金属层。 形成在第一图案化金属层上的电介质层分离两个金属层。 在介电层和第二图案化金属层上形成非导电层。

公开(公告)号：US20150236681A1

公开(公告)日：2015-08-20

申请号：US14249189

申请日：2014-04-09

Applicant: QUALCOMM Incorporated

Inventor： Hong Bok We ,  Dong Wook Kim ,  Kyu-Pyung Hwang ,  Young Kyu Song

IPC: H03K3/013 ,  H05K3/30 ,  H05K3/46 ,  G05F3/08 ,  H05K1/18 ,  H05K1/03

CPC classification number: H03K3/013 ,  G05F3/08 ,  H01L23/49822 ,  H01L23/50 ,  H01L24/13 ,  H01L24/16 ,  H01L2224/13147 ,  H01L2224/16225 ,  H01L2924/13091 ,  H01L2924/15311 ,  H05K1/0306 ,  H05K1/183 ,  H05K1/184 ,  H05K3/306 ,  H05K3/4697 ,  H05K2201/10015 ,  Y10T29/49139 ,  H01L2924/00

Abstract: An embedded multi-terminal capacitor embedded in a substrate cavity includes at least one metal layer patterned into a plurality of power rails and a plurality of ground rails. The substrate includes an external power network.

Abstract translation: 嵌入在衬底空腔中的嵌入式多端子电容器包括图案化成多个电源轨道和多个接地轨道的至少一个金属层。 基板包括外部电力网络。

公开(公告)号：US12021063B2

公开(公告)日：2024-06-25

申请号：US17161105

申请日：2021-01-28

Applicant: QUALCOMM Incorporated

Inventor： Joan Rey Villarba Buot ,  Aniket Patil ,  Zhijie Wang ,  Hong Bok We

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L25/00

CPC classification number: H01L25/0657 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49866 ,  H01L24/16 ,  H01L24/48 ,  H01L24/85 ,  H01L25/50 ,  H01L2224/16225 ,  H01L2224/48227 ,  H01L2224/48471 ,  H01L2224/85345

Abstract: Disclosed are examples of integrated circuit (IC) packages. Each IC package may include a flip-chip (FC) die on a substrate, a wire bond die above the FC die, a wire bond connected to the wire bond die, and a mold on the substrate and encapsulating the FC die, the wire bond die, and the wire bond. The substrate may include least a first metallization layer includes a first substrate layer, a trace on the first substrate layer and routed within the first metallization layer to electrically couple with one or more FC interconnects of the FC die, and a bond finger pad formed on the trace. The bond finger pad may be circular. The wire bond may electrically connect to the trace such that the wire bond die is electrically coupled with the FC die through the wire bond, the bond finger pad, and the trace.

公开(公告)号：US20240006369A1

公开(公告)日：2024-01-04

申请号：US17809675

申请日：2022-06-29

Applicant: QUALCOMM Incorporated

Inventor： Aniket Patil ,  Hong Bok We ,  Joan Rey Villarba Buot

IPC: H01L23/00 ,  H01L23/498 ,  H01L21/48

CPC classification number: H01L24/48 ,  H01L23/49822 ,  H01L23/49838 ,  H01L24/85 ,  H01L21/4853 ,  H01L21/4857 ,  H01L2224/48111 ,  H01L2924/19107

Abstract: Integrated circuit (IC) packages employing wire bond channel over package substrate, and related fabrication methods. The IC package includes a first semiconductor die (“first die”) and a first electronic device each coupled to a package substrate. To provide signal routing paths between the first die and the first electronic device, the IC package includes a wire bond channel that includes wire bonds coupled between first and second metal pads coupled to the respective first die and first electronic device to provide signal routing paths between the first die and first electronic device. The wire bonds extend outside of the package substrate in a vertical direction. The wire bond channel may be able to support more direct signal routing paths between the first die and the first electronic device without having to route such signal routing paths around a KoZ in the package substrate.

公开(公告)号：US11804645B2

公开(公告)日：2023-10-31

申请号：US17474524

申请日：2021-09-14

Applicant: QUALCOMM Incorporated

Inventor： Hong Bok We ,  Joan Rey Villarba Buot ,  Aniket Patil

IPC: H01Q1/22 ,  H01Q1/38 ,  H01Q1/42 ,  H01Q1/52 ,  H01Q9/04 ,  H01Q21/06

CPC classification number: H01Q1/2283 ,  H01Q1/38 ,  H01Q1/422 ,  H01Q1/526 ,  H01Q9/0414 ,  H01Q21/065

Abstract: Multi-sided antenna modules employing antennas on multiple sides of a package substrate for enhanced antenna coverage, and related antenna module fabrication methods. The multi-sided antenna module includes an integrated circuit (IC) die(s) disposed on a first side of the package substrate. The multi-sided antenna module further includes first and second substrate antenna layers disposed on respective first and second sides of the package substrate. The first substrate antenna layer includes a first antenna(s) disposed on the first side of the package substrate adjacent to the IC die(s). The second substrate antenna layer includes a second antenna(s) disposed on the second side of the package substrate opposite of the first side of the package substrate. In this manner, the multi-sided antenna module, including antennas on multiple sides of the package substrate, provides antenna coverage that extends from both sides of the package substrate to provide multiple directions of coverage.