公开(公告)号：US12021063B2

公开(公告)日：2024-06-25

申请号：US17161105

申请日：2021-01-28

Applicant: QUALCOMM Incorporated

Inventor： Joan Rey Villarba Buot ,  Aniket Patil ,  Zhijie Wang ,  Hong Bok We

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L25/00

CPC classification number: H01L25/0657 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49866 ,  H01L24/16 ,  H01L24/48 ,  H01L24/85 ,  H01L25/50 ,  H01L2224/16225 ,  H01L2224/48227 ,  H01L2224/48471 ,  H01L2224/85345

Abstract: Disclosed are examples of integrated circuit (IC) packages. Each IC package may include a flip-chip (FC) die on a substrate, a wire bond die above the FC die, a wire bond connected to the wire bond die, and a mold on the substrate and encapsulating the FC die, the wire bond die, and the wire bond. The substrate may include least a first metallization layer includes a first substrate layer, a trace on the first substrate layer and routed within the first metallization layer to electrically couple with one or more FC interconnects of the FC die, and a bond finger pad formed on the trace. The bond finger pad may be circular. The wire bond may electrically connect to the trace such that the wire bond die is electrically coupled with the FC die through the wire bond, the bond finger pad, and the trace.

公开(公告)号：US11545435B2

公开(公告)日：2023-01-03

申请号：US16946104

申请日：2020-06-05

Applicant: QUALCOMM Incorporated

Inventor： Kuiwon Kang ,  Zhijie Wang ,  Hong Bok We

IPC: H01L23/538 ,  H01L25/065 ,  H01L23/498

Abstract: Some features pertain to a substrate that includes a first portion of the substrate including a first plurality of metal layers, a second portion of the substrate including a second plurality of metal layers, and a plurality of insulating layers configured to separate the first plurality of metal layers and the second plurality of metal layers. A first plurality of posts and a plurality of interconnects are coupled together such that the first plurality of posts and the plurality of interconnects couple the first portion of the substrate to the second portion of the substrate.

公开(公告)号：US11302656B2

公开(公告)日：2022-04-12

申请号：US16938316

申请日：2020-07-24

Applicant: QUALCOMM Incorporated

Inventor： Hong Bok We ,  Aniket Patil ,  Joan Rey Villarba Buot ,  Zhijie Wang

IPC: H01L23/64 ,  H01L21/48 ,  H01L23/498 ,  H01L23/00 ,  H01L25/065

Abstract: An integrated circuit (IC) package is described. The IC package includes a package substrate, composed of a substrate core, a first power rail on a first surface of the substrate core, and a second power rail on a second surface of the substrate core. The IC package includes a logic die supported by the second power rail on the second surface of the substrate core. The IC package includes passive devices within the substrate core. Each of the passive devices has a first terminal and a second terminal opposite the first terminal. The first terminal of each of the passive devices is directly coupled to the first power rail, and the second terminal of each of the plurality of the passive devices is directly coupled to the second power rail. The IC package includes package bumps on the second power rail on the second surface of the substrate core.

公开(公告)号：US10971455B2

公开(公告)日：2021-04-06

申请号：US16400264

申请日：2019-05-01

Applicant: QUALCOMM Incorporated

Inventor： Aniket Patil ,  Kuiwon Kang ,  Zhijie Wang ,  Ming Yi

IPC: H01L23/552 ,  H01L23/04 ,  H01L23/49 ,  H01L23/498 ,  H01L21/52 ,  H01L23/556

Abstract: Certain aspects of the present disclosure provide an integrated circuit (IC) package and techniques for fabricating the IC package. The IC package generally includes a substrate, an IC disposed above the substrate, and a shielding layer coupled to a layer of the substrate, wherein the shielding layer is disposed above the substrate adjacent to the IC, and below an upper surface of the IC.

公开(公告)号：US20250062235A1

公开(公告)日：2025-02-20

申请号：US18450636

申请日：2023-08-16

Applicant: QUALCOMM Incorporated

Inventor： Joan Rey Villarba Buot ,  Hong Bok We ,  Zhijie Wang ,  Sang-Jae Lee

IPC: H01L23/538 ,  H01L21/48 ,  H01L25/16

Abstract: Package substrate with metallization layer(s) that includes an additional metal pad layer to facilitate reduced via size for reduced bump pitch, and related integrated circuit (IC) packages and fabrication methods. An additional metal pad(s) is provided in an insulating layer of a metallization layer(s) of the package substrate in which a via(s) is formed to reduce vertical connectivity distance between metal interconnects in adjacent metallization layers electrically coupled together by the via. This can reduce the aspect ratio and size of the via thereby allowing metal interconnects that are electrically coupled to the via to also be reduced in size (e.g., width) while still supporting an aligned, low resistance connection between the via(s) and the metal interconnects. Being able to reduce the size (e.g., width) of the metal interconnects can reduce bump pitch of the package substrate, which can facilitate a higher density of die/bump connections to the package substrate.

公开(公告)号：US20240332146A1

公开(公告)日：2024-10-03

申请号：US18193295

申请日：2023-03-30

Applicant: QUALCOMM Incorporated

Inventor： Joan Rey Villarba Buot ,  Hong Bok We ,  Zhijie Wang ,  Sang-Jae Lee

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/00 ,  H01L23/42 ,  H01L23/538

CPC classification number: H01L23/49811 ,  H01L21/4857 ,  H01L23/42 ,  H01L23/49822 ,  H01L23/49833 ,  H01L23/5383 ,  H01L24/83 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81 ,  H01L2224/83

Abstract: Integrated circuit (IC) package employing metal posts thermally coupling a die to an interposer substrate for dissipating thermal energy of the die are disclosed. In one aspect, the IC package includes a metal post(s) thermally coupled to the die. The metal post(s) is attached to metal interconnect(s) (e.g., metal trace, metal pad, metal line, metal plate) in the interposer substrate. In this manner, as thermal energy is generated in the die, this thermal energy dissipates through the metal post(s) and through the coupled metal interconnect(s) into the interposer substrate. Thus, metal interconnects, which are an available feature in an interposer substrate fabrication process, are deployed to form the foundation upon which metal posts are fabricated and thermally coupled to the die to provide heat dissipation for the die in the IC package.

公开(公告)号：US20230307336A1

公开(公告)日：2023-09-28

申请号：US17656477

申请日：2022-03-25

Applicant: QUALCOMM Incorporated

Inventor： Joan Rey Villarba Buot ,  Zhijie Wang ,  Aniket Patil ,  Hong Bok We

IPC: H01L23/498 ,  H01L21/48

CPC classification number: H01L23/49822 ,  H01L23/49894 ,  H01L21/4857

Abstract: Package substrates employing a pad metallization layer for increased signal routing capacity, and related integrated circuit (IC) packages and fabrication methods. To support increased signal routing density in an IC package while mitigating an increase in overall IC package thickness, an outer metallization layer of the package substrate is provided as a thinner, pad metallization layer. A metal layer in the pad metallization layer includes metal pads for forming external connections to the package substrate. This allows an area in the adjacent metallization layer that would otherwise have larger width metal pads for forming external interconnects, to be used for other signal routing within the package substrate. This can increase the overall signal routing density of the package substrate while mitigating the increase in overall package substrate thickness if a full-sized additional metallization layer were added to the package substrate.

公开(公告)号：US11581251B2

公开(公告)日：2023-02-14

申请号：US17093954

申请日：2020-11-10

Applicant: QUALCOMM Incorporated

Inventor： Aniket Patil ,  Zhijie Wang ,  Joan Rey Villarba Buot ,  Hong Bok We

IPC: H01L23/498 ,  H01L23/495 ,  H01L25/10 ,  H01L25/00

Abstract: A device comprising a first package and a second package coupled to the first package. The first package includes a first substrate, at least one gradient interconnect structure coupled to the first substrate, and a first integrated device coupled to the first substrate. The second package includes a second substrate and a second integrated device coupled to the second substrate. The second substrate is coupled to the at least one gradient interconnect structure.

公开(公告)号：US11322490B2

公开(公告)日：2022-05-03

申请号：US16851357

申请日：2020-04-17

Applicant: QUALCOMM Incorporated

Inventor： Joan Rey Villarba Buot ,  Zhijie Wang

IPC: H01L25/18 ,  H01L25/00 ,  H01G4/30 ,  H01L23/31 ,  H01L23/495 ,  H01L23/00 ,  H01L27/01 ,  H01L49/02

Abstract: Certain aspects of the present disclosure generally relate to a modular capacitor array, such as for an integrated circuit package, and methods for fabricating the same. One example integrated circuit package generally includes a package substrate, a semiconductor die disposed above the package substrate, and at least one modular capacitor array disposed below the package substrate. The modular capacitor array may be a pre-packaged array of capacitive elements, such as multi-layer ceramic capacitors (MLCCs).

公开(公告)号：US20240250009A1

公开(公告)日：2024-07-25

申请号：US18158225

申请日：2023-01-23

Applicant: QUALCOMM Incorporated

Inventor： Seongryul Choi ,  Joan Rey Villarba Buot ,  Kuiwon Kang ,  Zhijie Wang

IPC: H01L23/498 ,  H01L21/288 ,  H01L21/768 ,  H01L23/00

CPC classification number: H01L23/49838 ,  H01L21/288 ,  H01L21/76829 ,  H01L23/49816 ,  H01L24/04 ,  H01L24/08 ,  H01L24/16 ,  H01L24/48 ,  H01L2224/0401 ,  H01L2224/08112 ,  H01L2224/08225 ,  H01L2224/16014 ,  H01L2224/16113 ,  H01L2224/16227 ,  H01L2224/48105 ,  H01L2224/48225

Abstract: Embedded trace substrates (ETS) having an ETS metallization layer with T-shaped interconnects with reduced-width embedded metal traces, and related integrated circuit (IC) packages and fabrication methods. The ETS includes an outer ETS metallization layer that includes T-shaped interconnects for supporting input/output (I/O) connections between the ETS and another opposing package substrate. To increase density of I/O interconnections, the pitch of the embedded metal traces in the ETS metallization layer is reduced. The T-shaped interconnects also each include an additional metal contact pad that is coupled to a respective embedded metal trace to increase the height of the embedded metal trace to eliminate a vertical connection gap between the ETS and an opposing package substrate. In the T-shape interconnects, their embedded metal traces are reduced in width in a horizontal direction(s) as compared to their respective metal contact pads to provide room for additional metal traces for additional signal routing capacity.