公开(公告)号：US20240250009A1

公开(公告)日：2024-07-25

申请号：US18158225

申请日：2023-01-23

申请人： QUALCOMM Incorporated

发明人： Seongryul Choi ,  Joan Rey Villarba Buot ,  Kuiwon Kang ,  Zhijie Wang

IPC分类号： H01L23/498 ,  H01L21/288 ,  H01L21/768 ,  H01L23/00

CPC分类号： H01L23/49838 ,  H01L21/288 ,  H01L21/76829 ,  H01L23/49816 ,  H01L24/04 ,  H01L24/08 ,  H01L24/16 ,  H01L24/48 ,  H01L2224/0401 ,  H01L2224/08112 ,  H01L2224/08225 ,  H01L2224/16014 ,  H01L2224/16113 ,  H01L2224/16227 ,  H01L2224/48105 ,  H01L2224/48225

摘要： Embedded trace substrates (ETS) having an ETS metallization layer with T-shaped interconnects with reduced-width embedded metal traces, and related integrated circuit (IC) packages and fabrication methods. The ETS includes an outer ETS metallization layer that includes T-shaped interconnects for supporting input/output (I/O) connections between the ETS and another opposing package substrate. To increase density of I/O interconnections, the pitch of the embedded metal traces in the ETS metallization layer is reduced. The T-shaped interconnects also each include an additional metal contact pad that is coupled to a respective embedded metal trace to increase the height of the embedded metal trace to eliminate a vertical connection gap between the ETS and an opposing package substrate. In the T-shape interconnects, their embedded metal traces are reduced in width in a horizontal direction(s) as compared to their respective metal contact pads to provide room for additional metal traces for additional signal routing capacity.

公开(公告)号：US11764076B2

公开(公告)日：2023-09-19

申请号：US17107512

申请日：2020-11-30

申请人： QUALCOMM Incorporated

发明人： Kuiwon Kang ,  Joan Rey Villarba Buot ,  Terence Cheung

IPC分类号： H01L21/48 ,  H01L23/498 ,  H01L23/00

CPC分类号： H01L21/4857 ,  H01L21/481 ,  H01L23/49822 ,  H01L23/49838 ,  H01L24/16 ,  H01L2224/16227 ,  H01L2224/16238

摘要： Certain aspects of the present disclosure generally relate to an embedded trace substrate with partially buried traces, methods for fabrication thereof, and apparatus comprising such an embedded trace substrate. One example method of fabricating an embedded trace substrate generally includes creating a pattern of conductive traces above a dielectric layer and mechanically pressing on the pattern of conductive traces such that lower portions of the conductive traces are buried in the dielectric layer.

公开(公告)号：US11637057B2

公开(公告)日：2023-04-25

申请号：US16724247

申请日：2019-12-21

申请人： QUALCOMM Incorporated

发明人： Kuiwon Kang ,  Chin-Kwan Kim ,  Aniket Patil ,  Jaehyun Yeon

IPC分类号： H01L23/498 ,  H01L21/48

摘要： Examples herein provide more integrated circuit packages that allow direct bonding of semiconductor chips to the package, smaller line/spacing of traces, and uniform vias with no capture or cover pads. For example, an integrated circuit (IC) package may include a plurality of pads and a plurality of traces on a substrate with at least two of the plurality of traces located between two of the plurality of pads, and a dielectric layer that completely covers the plurality of traces and partially covers the plurality of pads.

公开(公告)号：US20230114404A1

公开(公告)日：2023-04-13

申请号：US17822589

申请日：2022-08-26

申请人： QUALCOMM Incorporated

发明人： Seongryul Choi ,  Kuiwon Kang ,  Joan Rey Villarba Buot

IPC分类号： H01L23/538 ,  H01L25/10 ,  H01L23/00 ,  H01L21/48 ,  H01L23/498

摘要： Embedded trace substrate (ETS) with embedded metal traces having multiple thicknesses for integrated circuit (IC) package height control, and related IC packages and fabrication methods. The IC package includes a die that is coupled to a package substrate to provide signal routing paths to the die. The IC package also includes an ETS that includes metal traces embedded in an insulating layer(s) to provide connections for signal routing paths for the IC package. To control (such as to reduce) the height of the IC package, the embedded metal traces embedded in an insulating layer in the ETS are provided to have multiple thicknesses (i.e., heights) in a vertical direction. The embedded metal traces in the ETS whose thicknesses affect the overall height of the IC package by being coupled to interconnects external to the ETS in the vertical direction, can be reduced in thickness to control IC package height.

公开(公告)号：US10679919B2

公开(公告)日：2020-06-09

申请号：US16016888

申请日：2018-06-25

申请人： QUALCOMM Incorporated

发明人： Kuiwon Kang ,  Zhijie Wang ,  Bohan Yan

IPC分类号： H01L23/498 ,  H01L23/00 ,  H01L23/367 ,  H01L23/373

摘要： An integrated circuit package having an interposer with increased thermal conductivity and techniques for fabricating such an integrated circuit package are provided. One example integrated circuit package generally includes a package substrate, at least one semiconductor die disposed above the package substrate, and an interposer disposed above the at least one semiconductor die. The interposer includes a dielectric layer, and a metallic plate disposed adjacent to a first portion of the dielectric layer. The height of the metallic plate is greater than a height of the dielectric layer.

公开(公告)号：US11776888B2

公开(公告)日：2023-10-03

申请号：US17334610

申请日：2021-05-28

申请人： QUALCOMM Incorporated

发明人： Kuiwon Kang ,  Hong Bok We ,  Chin-Kwan Kim ,  Milind Shah

IPC分类号： H01L23/498 ,  H01L21/48 ,  H01L23/00

CPC分类号： H01L23/49838 ,  H01L21/4853 ,  H01L21/4857 ,  H01L23/49822 ,  H01L24/16 ,  H01L2224/16227 ,  H01L2224/16238

摘要： A package comprising a substrate and an integrated device coupled to the substrate. The substrate includes at least one dielectric layer, a plurality of interconnects comprising a plurality of protruding pad interconnects, and a solder resist layer located over the at least one dielectric layer, the solder resist layer comprising a thickness that is greater than a thickness of the plurality of protruding pad interconnects. A protruding pad interconnect may include a first pad portion and a second pad portion.

公开(公告)号：US11605595B2

公开(公告)日：2023-03-14

申请号：US16994398

申请日：2020-08-14

申请人： QUALCOMM Incorporated

发明人： Aniket Patil ,  Hong Bok We ,  Kuiwon Kang

IPC分类号： H01L23/538 ,  H01L21/48

摘要： Disclosed is an apparatus and methods for making same. The apparatus includes a first insulating layer, a first metal layer disposed on a surface of the first insulating layer, and a metallization structure embedded in the first insulating layer. The metallization structure occupies only a portion of a volume of the first insulating layer. The metallization structure has a line density greater than a line density of the first metal layer.

公开(公告)号：US20220068780A1

公开(公告)日：2022-03-03

申请号：US17405494

申请日：2021-08-18

申请人： QUALCOMM Incorporated

发明人： Kuiwon Kang ,  Chin-Kwan Kim ,  Joonsuk Park

IPC分类号： H01L23/498 ,  H01L23/00 ,  H01L21/48

摘要： Integrated circuit (IC) package substrate with an embedded trace substrate (ETS) layer on a substrate, and related fabrication methods. The package substrate of the IC package includes an ETS layer provided on the substrate to facilitate providing higher density substrate interconnects to provide bump/solder joints for coupling a semiconductor die to the package substrate. ETS interconnects in the ETS layer in the package substrate facilitates die connections having a reduced line-spacing ratio (L/S) (e.g., 5.0 micrometers (μm)/5.0 μm or less) over substrate interconnects in a substrate. In additional exemplary aspects, raised metal pillar interconnects are formed in contact with respective ETS interconnects of the ETS layer of the package substrate to avoid or reduce metal consumption by die solder disposed on metal pillar interconnects of the ETS layer providing bump/solder joints.

公开(公告)号：US11075260B2

公开(公告)日：2021-07-27

申请号：US16176915

申请日：2018-10-31

申请人： QUALCOMM Incorporated

发明人： Kuiwon Kang ,  Chin-Kwan Kim ,  Hong Bok We ,  Jaehyun Yeon

IPC分类号： H01L23/498 ,  H01L49/02 ,  H01L21/56 ,  H01L23/31

摘要： A device that includes a substrate, a die, and a discrete capacitor. The substrate includes a dielectric layer and a plurality of interconnects formed in the dielectric layer. The discrete capacitor is coupled to the substrate through a first solder interconnect and a second solder interconnect. The first solder interconnect and the second solder interconnect are located within the dielectric layer. The die is coupled to the substrate. In some implementations, the first solder interconnect is located in a first cavity of the dielectric layer, and the second solder interconnect is located in a second cavity of the dielectric layer. In some implementations, the substrate includes a first cavity that is filled with a first via and the first solder interconnect; and a second cavity that is filled with a second via and the second solder interconnect.

公开(公告)号：US09679841B2

公开(公告)日：2017-06-13

申请号：US14276763

申请日：2014-05-13

申请人： QUALCOMM Incorporated

发明人： Houssam Wafic Jomaa ,  Omar James Bchir ,  Kuiwon Kang ,  Chin-Kwan Kim

IPC分类号： H01L23/535 ,  H01L23/522 ,  H01L21/768 ,  H01L21/48 ,  H01L23/538 ,  H01L21/683

CPC分类号： H01L23/5226 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/6835 ,  H01L21/76877 ,  H01L21/76895 ,  H01L23/5383 ,  H01L23/5384 ,  H01L2221/68345 ,  H01L2924/0002 ,  H01L2924/00

摘要： Methods and apparatus for formation of a semiconductor substrate with photoactive dielectric material, embedded traces, a padless skip via extending through two dielectric layers, and a coreless package are provided. In one embodiment, a method for forming a core having a copper layer; laminating the copper layer a photoactive dielectric layer; forming a plurality of trace patterns in the photoactive dielectric layer; plating the plurality of trace patterns to form a plurality of traces; forming an insulating dielectric layer on the photoactive dielectric layer; forming a via through the insulating dielectric layer and the photoactive dielectric layer; forming additional routing patterns on the insulating dielectric layer; removing the core; and applying a solder mask.