公开(公告)号：US11764076B2

公开(公告)日：2023-09-19

申请号：US17107512

申请日：2020-11-30

申请人： QUALCOMM Incorporated

发明人： Kuiwon Kang ,  Joan Rey Villarba Buot ,  Terence Cheung

IPC分类号： H01L21/48 ,  H01L23/498 ,  H01L23/00

CPC分类号： H01L21/4857 ,  H01L21/481 ,  H01L23/49822 ,  H01L23/49838 ,  H01L24/16 ,  H01L2224/16227 ,  H01L2224/16238

摘要： Certain aspects of the present disclosure generally relate to an embedded trace substrate with partially buried traces, methods for fabrication thereof, and apparatus comprising such an embedded trace substrate. One example method of fabricating an embedded trace substrate generally includes creating a pattern of conductive traces above a dielectric layer and mechanically pressing on the pattern of conductive traces such that lower portions of the conductive traces are buried in the dielectric layer.

公开(公告)号：US11552023B2

公开(公告)日：2023-01-10

申请号：US16913288

申请日：2020-06-26

申请人： QUALCOMM Incorporated

发明人： Kuiwon Kang ,  Brigham Navaja ,  Marcus Hsu ,  Terence Cheung

IPC分类号： H01L23/538 ,  H01L23/498 ,  H01L23/522 ,  H01L21/768 ,  H01L21/48 ,  H01L49/02

摘要： Certain aspects of the present disclosure generally relate to an embedded trace substrate (ETS) with one or more passive components embedded therein. Such an ETS may provide shorter routing, smaller loop area, and lower parasitics between a semiconductor die and a land-side passive component embedded in the ETS. One example embedded trace substrate generally includes a core, a first insulating material disposed above the core and having a first metal pattern embedded therein, a second insulating material disposed below the core and having a second metal pattern embedded therein, and one or more passive components embedded in the core.

公开(公告)号：US11437307B2

公开(公告)日：2022-09-06

申请号：US16949695

申请日：2020-11-11

申请人： QUALCOMM Incorporated

发明人： Abdolreza Langari ,  Yuan Li ,  Shrestha Ganguly ,  Terence Cheung ,  Ching-Liou Huang ,  Hui Wang

IPC分类号： H01L23/495 ,  H01L23/498 ,  H01L23/538 ,  H01L25/18 ,  H01L23/00 ,  H01L21/48 ,  H01L25/00

摘要： A device that includes a first die and a package substrate. The package substrate includes a dielectric layer, a plurality of vias formed in the dielectric layer, a first plurality of interconnects formed on a first metal layer of the package substrate, and a second plurality of interconnects formed on a second metal layer of the package substrate. The device includes a first series of first solder interconnects arranged in a first direction, the first series of first solder interconnects configured to provide a first electrical connection; a second series of first solder interconnects arranged in the first direction, the second series of first solder interconnects configured to provide a second electrical connection; a first series of second solder interconnects arranged in a second direction, the first series of second solder interconnects configured to provide the first electrical connection.

公开(公告)号：US10916494B2

公开(公告)日：2021-02-09

申请号：US16453803

申请日：2019-06-26

申请人： QUALCOMM Incorporated

发明人： Abdolreza Langari ,  Yuan Li ,  Shrestha Ganguly ,  Terence Cheung ,  Ching-Liou Huang ,  Hui Wang

IPC分类号： H01L23/498 ,  H01L23/538 ,  H01L25/18 ,  H01L23/00 ,  H01L21/48 ,  H01L25/00

摘要： A device that includes a first die and a package substrate. The package substrate includes a dielectric layer, a plurality of vias formed in the dielectric layer, a first plurality of interconnects formed on a first metal layer of the package substrate, and a second plurality of interconnects formed on a second metal layer of the package substrate. The device includes a first series of first solder interconnects arranged in a first direction, the first series of first solder interconnects configured to provide a first electrical connection; a second series of first solder interconnects arranged in the first direction, the second series of first solder interconnects configured to provide a second electrical connection; a first series of second solder interconnects arranged in a second direction, the first series of second solder interconnects configured to provide the first electrical connection.